Time-to-voltage converter using a capacitor based digital to analog converter for quantization noise cancellation
AssigneeSilicon Laboratories Inc.
InventorMichael H. Perrott
Life of this patent
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Abstract
Quantization noise in a fractional-N phase-locked loop (PLL) is canceled using a capacitor-based digital to analog converter (DAC). A phase error is detected between a reference signal and a feedback signal in the PLL. A charge pump circuit charges a first capacitor circuit based on the phase error to generate a phase error voltage corresponding to the phase error. The capacitor based DAC generates a quantization error correction voltage based on a digital value corresponding to the quantization error, which is then combined with the phase error voltage to cancel the quantization error.
Claims25
A phase-locked loop (PLL) comprising:
- a capacitor based digital to analog converter (DAC) coupled to receive a digital indication of quantization noise and to supply a quantization noise correction voltage to adjust a phase error voltage to create a combined voltage with reduced quantization noise, wherein the phase error voltage is indicative of a phase error corresponding to a time difference between a reference signal and a feedback signal from an oscillator controlled at least in part based on a value of the combined voltage.
A method comprising:
- cancelling quantization noise in a fractional-N phase-locked loop (PLL) using a capacitor-based digital to analog converter (DAC).
A capacitor based digital to analog converter (DAC) comprising:
- a storage circuit;
- a plurality of capacitors coupled between the storage circuit storing respective digital bits for each of the capacitors and a first node;
- a first switch to selectively couple the first node to a first voltage according to a first control signal;
- a second switch to selectively couple the first node to a second voltage according to a second control signal;
- and
- wherein the storage circuit is coupled to be set or reset according to a state of the first and second control signals;
- wherein the capacitor DAC is precharged to a first or second state according to the first and second control signals.
Dependencies are inferred from the claim text.