Germanium FinFETs with metal gates and stressors
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih Chieh Yeh, Chih-Sheng Chang, Clement Hsingjen Wann
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Abstract
An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.
Claims19
An integrated circuit structure comprising:
- a substrate comprising silicon;
- shallow trench isolation (STI) regions extending into the substrate;
- an n-type fin field effect transistor (FinFET) comprising:
- a first germanium fin over top surfaces of the STI regions;
- a first gate dielectric on a top surface and sidewalls of the first germanium fin;
- a first gate electrode on the first gate dielectric;
- and
- a source/drain region comprising germanium, with a germanium atomic percentage in the source/drain region being lower than a germanium atomic percentage in the first germanium fin, and the source/drain region extends below the top surfaces of the STI regions to contact the substrate;
- a p-type FinFET comprising:
- a second germanium fin over the substrate, wherein the first germanium fin and the second germanium fin are pure germanium fins;
- a second gate dielectric on a top surface and sidewalls of the second germanium fin;
- and
- a second gate electrode on the second gate dielectric, wherein the first gate electrode and the second gate electrode are formed of a same material having a work function between 4.25 eV and 4.4 eV.
An integrated circuit structure comprising:
- a substrate comprising silicon;
- shallow trench isolation (STI) regions extending into the substrate;
- a p-type fin field effect transistor (FinFET) comprising:
- a first germanium fin over the substrate;
- a first gate dielectric on a top surface and sidewalls of the first germanium fin;
- a first metal gate on the first gate dielectric;
- and
- a first source/drain region adjacent the first metal gate, wherein the first source/drain comprises a first epitaxial region formed of a semiconductor material different from the first germanium fin;
- and
- an n-type FinFET comprising:
- a second germanium fin over the substrate;
- a second gate dielectric on a top surface and sidewalls of the second germanium fin;
- a second metal gate on the second gate dielectric, wherein the first metal gate and the second metal gate are formed of a same material;
- and
- a second source/drain region adjacent the second metal gate, with the second source/drain region comprising germanium, and a germanium atomic percentage in the second source/drain region being lower than a germanium atomic percentage in the first germanium fin, wherein a bottom surface of the second source/drain region extends below the top surfaces of the STI regions to contact the substrate.
An integrated circuit structure comprising:
- a substrate;
- shallow trench isolation (STI) regions extending into the substrate;
- a p-type fin field effect transistor (FinFET) comprising:
- a first germanium fin over the substrate, wherein the first germanium fin is a germanium fin without being doped with silicon;
- a first gate dielectric on a top surface and sidewalls of the first germanium fin;
- a first metal gate on the first gate dielectric;
- and
- a first source/drain region adjacent to the first metal gate;
- and
- an n-type FinFET comprising:
- a second germanium fin over the substrate, wherein the second germanium fin is a germanium fin without being doped with silicon;
- a second gate dielectric on a top surface and sidewalls of the second germanium fin;
- a second metal gate on the second gate dielectric;
- and
- a second source/drain region adjacent to the second metal gate, wherein the second source/drain region comprises silicon germanium, with a germanium atomic percentage in the second source/drain region being lower than a germanium atomic percentage in the second germanium fin, wherein the second source/drain region extends below the top surfaces of the STI regions to contact the substrate.
Dependencies are inferred from the claim text.