Methods for improving flow cache bandwidth utilization and devices thereof

A network traffic management apparatus, comprising:

• a first memory comprising a flow cache table including a plurality of entries, each of the plurality of entries including a flow specification and transformation data;
• and
• configurable hardware logic coupled to the first memory and a processor, the configurable hardware logic comprising a valid split table including a plurality of entries, wherein each of the plurality of entries of the valid split table includes a validity bit and the configurable hardware logic is configured to implement:
• obtaining a network packet having an associated flow specification;
• generating an index value based at least in part on at least a portion of the flow specification associated with the obtained network packet;
• determining whether the validity bit of one of the plurality of entries of the valid split table corresponding to the index value is set;
• retrieving one of the plurality of entries of the flow cache table corresponding to the index value, when it is determined that the validity bit of the one of the plurality of entries of the valid split table corresponding to the index value is set;
• determining whether the flow specification associated with the obtained network packet matches the flow specification of the retrieved one of the plurality of entries of the flow cache table;
• transforming the network packet based on the transformation data of the retrieved one of the plurality of entries of the flow cache table, when it is determined that the flow specification associated with the obtained network packet matches the flow specification of the retrieved one of the plurality of entries of the flow cache table;
• and
• communicating the transformed network packet to an external network device.

A network traffic management apparatus, comprising:

• a first memory comprising a flow cache table including a plurality of entries;
• and
• configurable hardware logic coupled to the first memory and a processor and comprising a recently hit split table including a plurality of entries, wherein each of the plurality of entries of the recently hit split table includes a recently hit bit and the configurable hardware logic is configured to implement:
• periodically determining whether the recently hit bit of each of the plurality of entries of the recently hit split table is set;
• and
• retrieving one of the plurality of entries of the flow cache table corresponding to an index value associated with one of the plurality of entries of the recently hit split table, when it is determined that the recently hit bit of the one of the plurality of entries of the recently hit split table is not set.