Microprocessor that translates conditional load/store instructions into variable number of microinstructions

A method for operating a microprocessor having condition flags, the method comprising:

• receiving a conditional load/store instruction that specifies a condition, a destination/data register, a base register, an offset source, and a memory addressing mode, wherein the instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load instruction) or store data to the memory location from the data register (conditional store instruction) only if the condition flags satisfy the condition, wherein the offset source specifies whether the offset is an immediate value or a value in an offset register, wherein the addressing mode specifies whether or not the base register is updated when the condition flags satisfy the condition;
• translating the conditional load instruction into a number of microinstructions, wherein the number of microinstructions varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction;
• and
• executing the microinstructions to generate results specified by the instruction, by an out-of-order execution pipeline.

A computer program product encoded in at least one computer readable storage medium for use with a computing device, the computer program product comprising:

• computer readable program code embodied in said medium, for specifying a microprocessor, the computer readable program code comprising:
• first program code for specifying condition flags;
• second program code for specifying an instruction translator, that receives a conditional load/store instruction that specifies a condition, a destination/data register, a base register, an offset source, and a memory addressing mode, wherein the instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load instruction) or store data to the memory location from the data register (conditional store instruction) only if the condition flags satisfy the condition, wherein the offset source specifies whether the offset is an immediate value or a value in an offset register, wherein the addressing mode specifies whether or not the base register is updated when the condition flags satisfy the condition, wherein the instruction translator translates the conditional load instruction into a number of microinstructions, wherein the number of microinstructions varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction;
• and
• third program code for specifying an out-of-order execution pipeline, that executes the microinstructions to generate results specified by the instruction.