Back to results
US 9,240,495 B2Granted
Methods of forming nanoscale floating gate
AssigneeMicron Technology, Inc.
InventorsGurtej S. Sandhu, D. V. Nirmal Ramaswamy
Life of this patent
Estimating the term…
Abstract
A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.
Claims20
A memory cell, comprising:
- a charge storage structure, wherein the charge storage structure comprises:
- a first conductive portion over a tunnel dielectric overlying a semiconductor substrate;
- isolation regions, wherein the first conductive portion and a second conductive portion are between the isolation regions;
- and
- the second conductive portion, directly in contact with the first conductive portion, comprising at least one of a nanowire, nanotube, or a nanoribbon having an elongate structure extending over the first conductive portion and between and above a top of the isolation regions in an approximately perpendicular direction relative to a surface of the tunnel dielectric.
2 more elements
A memory cell, comprising:
- a charge storage structure, wherein the charge storage structure comprises:
- a first conductive portion over a tunnel dielectric overlying a semiconductor substrate;
- isolation regions, wherein the first conductive portion and a second conductive portion are between the isolation regions;
- and
- a second conductive portion, directly in contact with the first conductive portion, comprising at least one of a nanowire, nanotube, or a nanoribbon having a longest dimension extending from the first conductive portion in an approximately perpendicular direction relative to a surface of the tunnel dielectric, wherein there is one of the at least one of a nanowire, nanotube, or nanoribbon between a pair of the isolation regions.
2 more elements
A memory cell, comprising:
- a charge storage structure, wherein the charge storage structure comprises:
- a first conductive portion over a tunnel dielectric overlying a semiconductor substrate;
- isolation regions, wherein the first conductive portion and a second conductive portion are between the isolation regions;
- and
- a second conductive portion, directly in contact with the first conductive portion, comprising a nanorod having a cross section configured to be one of circular, rectangular, polygonal, or elliptical and having a longest dimension extending from the first conductive portion and between and above a top of the isolation regions in an approximately perpendicular direction relative to a surface of the tunnel dielectric;
- wherein:
- there is one of the at least one of a nanowire, nanotube, or nanoribbon between a pair of the isolation regions;
- and
- the first conductive portion has a width dimension greater than a width dimension of the second conductive portion.
6 more elements
Dependencies are inferred from the claim text.