Transverse ultra-thin insulated gate bipolar transistor having high current density

A transverse ultra-thin insulated gate bipolar transistor having high current density, comprising:

• a P substrate (1), wherein the P substrate (1) is provided with a buried oxide layer (2) thereon, the buried oxide layer (2) is provided with an N epitaxial layer (3) thereon, the thickness of the N epitaxial layer (3) is 0.1 to 1.5 μm, the N epitaxial layer (3) is provided with an N well region (4) and a P base region (6a) therein, the N well region (4) is provided with an N buffer region (5) therein, the N well region (4) is provided with a field oxide layer (11) thereon, a boundary of the N buffer region (5) abuts against a boundary of the field oxide layer (11), the N buffer region (5) is provided with a P drain region (9) therein, and the P base region (6a) is provided with a first P contact region (7a) and an N source region (8a) therein, wherein the N epitaxial layer (3) is provided therein with a P base region array (17) comprising a P annular base region (6b), the P base region array (17) is located between the N well region (4) and the P base region (6a), the P annular base region (6b) is provided with a second P contact region (7b) and an N annular source region (8b) therein, the second P contact region (7b) is located in the N annular source region (8b), a first polysilicon gate (12a) is disposed on a surface of a boundary region on which the field oxide layer (11) and the N annular source region (8b) are adjacent, the first polysilicon gate (12) extends from the boundary of the field oxide layer (11) towards a direction of the N annular source region (8b) to a place above the N annular source region (8b), a first gate oxide layer (10a) is disposed below an extension region of the first polysilicon gate (12a), a second polysilicon gate (12b) is disposed above the N epitaxial layer (3), a boundary of the second polysilicon gate (12b) extends to the place above the N annular source region (8b), another boundary of the second polysilicon gate (12b) extends to a place above the N source region (8a), a second gate oxide layer (10b) is disposed below the second polysilicon gate (12b), a dielectric isolation oxide layer (13) is disposed on the field oxide layer (11), the first polysilicon gate (12a), the second polysilicon gate (12b), the P base region (6a), the P annular base region (6b), the first P contact region (7a), the N source region (8a), the second P contact region (7b), the N annular source region (8b), the N buffer region (5), and the P drain region (9), an emitter metal wire (14) is connected to the first P contact region (7a), the N source region (8a), the second P contact region (7b), and the N annular source region (8b), a collector metal wire (15) is connected to the P drain region (9), and a gate metal wire (16) is connected to the first polysilicon gate (12a) and the second polysilicon gate (12b).