# US 9,240,242 B1 · Method for operating low-cost EEPROM array

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- Number: US 9,240,242 B1
- Document ID: US9240242B1
- Status: Granted
- Kind: B1
- Application number: 14/565,644
- Filed: 2014-12-10
- Granted: 2016-01-19
- Earliest claimed: 2014-12-10
- Assignees: Yield Microelectronics Corp.
- Applicants: Yield Microelectronics Corp.
- Inventors: Hsin-Chang Lin; Wen-Chien Huang; Ya-Ting Fan; Yang-Sen Yeh; Cheng-Ying Wu
- Web page: https://patentgrep.com/patent/US9240242B1

## CPC

- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- G11C 16/10: Programming or data input circuits
- G11C 16/107: {Programming all cells in an array, sector or block to the same state prior to flash erasing}
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/24: Bit-line control circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for operating a low-cost EEPROM array is disclosed. The EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line and a second word line. The common source lines include a first common source line. Each sub-memory array includes a first memory cell and a second memory cell, which are respectively connected with the first and second word lines. Each of the first and second memory cells is also connected with the first bit line group and the first common source line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method operates all the operation memory cells and uses special biases to program or erase memory cells massively in a single operation.

## Claims

### Claim 1

A method for operating a low-cost electrically erasable programmable read only memory array, wherein said low-cost electrically erasable programmable read only memory (EEPROM) array comprises a plurality of parallel bit lines; a plurality of parallel word lines; a plurality of parallel common source lines; and a plurality of sub-memory arrays, and wherein said bit lines are divided into a plurality of bit line groups including a first bit line group, and wherein said word lines are vertical to said bit lines and include a first word line and a second word line, and wherein said common source lines are parallel to said word lines and include a first common source line, and wherein each said sub-memory array is connected with one said bit line group, two said word lines and one said common source line, and wherein each said sub-memory array includes a first memory cell and a second memory cell, and wherein said first memory cell is connected with said first bit line group, said first common source line and said first word line, and wherein said second memory cell is connected with said first bit line group, said first common source line and said second word line, and wherein said first memory cell and said second memory cell are symmetrically arranged at two sides of said first common source line, and wherein each of said first memory cell and said second memory cell has an N-type field-effect transistor (FET) built in a P-type substrate or a P-type well, and wherein each of said first memory cell and said second memory cell is an operation memory cell, and wherein in operating all said operation memory cells, said method is characterized in
that a substrate voltage Vsub is applied to said P-type substrate or said P-type well, which is connected with all said operation memory cells, and
that a bit voltage Vb, a word voltage Vw and a common source voltage Vs are respectively applied to all said bit lines, said word lines and said common source lines, which are connected with all said operation memory cells, and
that in writing, following conditions must be satisfied:
Vsub is grounded,
Vs=Vb=0, and
Vw=HV (High Voltage); and
that in erasing, following conditions must be satisfied:
Vsub is grounded,
Vs=Vb=HV, and
Vw is floating.

### Claim 2 (depends on 1)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 1, wherein said first bit line group includes one said bit line, which is connected with said first memory cell and said second memory cell.

### Claim 3 (depends on 1)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 1, wherein said first bit line group includes two said bit lines, which are respectively connected with said first memory cell and said second memory cell.

### Claim 4 (depends on 2)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 2, wherein two said second memory cells of two adjacent said sub-memory arrays are neighboring and share one common said bit line and a common contact.

### Claim 5 (depends on 3)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 3, wherein two said second memory cells of two adjacent said sub-memory arrays are neighboring and share one common said bit line and a common contact.

### Claim 6 (depends on 1)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 1, wherein said N-type FET of said first memory cell has a floating gate, a drain connected with said first bit line group, and a source connected with said first common source, and wherein said first memory cell also has a capacitor, and wherein one terminal of said capacitor is connected with said floating gate, and wherein another terminal of said capacitor is connected with said first word line to receive a bias from said first word line, and wherein said N-type FET receives a bias from said first bit line group and receives a bias from said first common source line to write data into or erase data from said floating gate of said N-type FET.

### Claim 7 (depends on 1)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 1, wherein said N-type FET of said second memory cell has a floating gate, a drain connected with said first bit line group, and a source connected with said first common source, and wherein said second memory cell also has a capacitor, and wherein one terminal of said capacitor is connected with said floating gate, and wherein another terminal of said capacitor is connected with said second word line to receive a bias from said second word line, and wherein said N-type FET receives a bias from said first bit line group and receives a bias from said first common source line to write data into or erase data from said floating gate of said N-type FET.

### Claim 8 (depends on 6)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 6, wherein an oxide layer and a control gate are formed above said floating gate in sequence, and wherein said control gate, said oxide layer and said floating gate jointly form a capacitor, and wherein said floating gate and said control gate are made of polysilicon.

### Claim 9 (depends on 7)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 7, wherein an oxide layer and a control gate are formed above said floating gate in sequence, and wherein said control gate, said oxide layer and said floating gate jointly form a capacitor, and wherein said floating gate and said control gate are made of polysilicon.

### Claim 10 (depends on 3)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 3, wherein said first word line and said second word line of an identical said sub-memory array are connected with an identical said word voltage.

### Claim 11

A method for operating a low-cost electrically erasable programmable read only memory array, wherein said low-cost electrically erasable programmable read only memory (EEPROM) array comprises a plurality of parallel bit lines; a plurality of parallel word lines; a plurality of parallel common source lines; and a plurality of sub-memory arrays, and wherein said bit lines are divided into a plurality of bit line groups including a first bit line group, and wherein said word lines are vertical to said bit lines and include a first word line and a second word line, and wherein said common source lines are parallel to said word lines and include a first common source line, and wherein one said sub-memory array is connected with one said bit line group, two said word lines and one said common source line, and wherein each said sub-memory array includes a first memory cell and a second memory cell, and wherein said first memory cell is connected with said first bit line group, said first common source line and said first word line, and wherein said second memory cell is connected with said first bit line group, said first common source line and said second word line, and wherein said first memory cell and said second memory cell are symmetrically arranged at two sides of said first common source line, and wherein each of said first memory cell and said second memory cell has a P-type field-effect transistor (FET) built in an N-type substrate or an N-type well, and wherein each of said first memory cell and said second memory cell is an operation memory cell, and wherein in operating all said operation memory cells, said method is characterized in that a substrate voltage Vsub is applied to said N-type substrate or said N-type well, which is connected with all said operation memory cells, and
that a bit voltage Vb, a word voltage Vw and a common source voltage Vs are respectively applied to all said bit lines, said word lines and said common source lines, which are connected with all said operation memory cells, and
that in writing, following conditions must be satisfied:
Vsub HV (High Voltage),
Vs=Vb=HV, and
Vw=0; and
that in erasing, following conditions must be satisfied:
Vsub=HV,
Vs=Vb=0, and
Vw is floating.

### Claim 12 (depends on 11)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 11, wherein aid first bit line group includes one said bit line, which is connected with said first memory cell and said second memory cell.

### Claim 13 (depends on 11)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 11, wherein said first bit line group includes two said bit lines, which are respectively connected with said first memory cell and said second memory cell.

### Claim 14 (depends on 12)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 12, wherein two said second memory cells of two adjacent said sub-memory arrays are neighboring and share one common said bit line and a common contact.

### Claim 15 (depends on 13)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 13, wherein two said second memory cells of two adjacent said sub-memory arrays are neighboring and share one common said bit line and a common contact.

### Claim 16 (depends on 11)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 11, wherein said P-type FET of said first memory cell has a floating gate, a drain connected with said first bit line group, and a source connected with said first common source, and wherein said first memory cell also has a capacitor, and wherein one terminal of said capacitor is connected with said floating gate, and wherein another terminal of said capacitor is connected with said first word line to receive a bias from said first word line, and wherein said P-type FET receives a bias from said first bit line group and receives a bias from said first common source line to write data into or erase data from said floating gate of said P-type FET.

### Claim 17 (depends on 11)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 11, wherein said P-type FET of said second memory cell has a floating gate, a drain connected with said first bit line group, and a source connected with said first common source, and wherein said second memory cell also has a capacitor, and wherein one terminal of said capacitor is connected with said floating gate, and wherein another terminal of said capacitor is connected with said second word line to receive a bias from said second word line, and wherein said P-type FET receives a bias from said first bit line group and receives a bias from said first common source line to write data into or erase data from said floating gate of said P-type FET.

### Claim 18 (depends on 16)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 16, wherein an oxide layer and a control gate are formed above said floating gate in sequence, and wherein said control gate, said oxide layer and said floating gate jointly form a capacitor, and wherein said floating gate and said control gate are made of polysilicon.

### Claim 19 (depends on 17)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 17, wherein an oxide layer and a control gate are formed above said floating gate in sequence, and wherein said control gate, said oxide layer and said floating gate jointly form a capacitor, and wherein said floating gate and said control gate are made of polysilicon.

### Claim 20 (depends on 13)

The method for operating a low-cost electrically erasable programmable read only memory array according to claim 13, wherein said first word line and said second word line of an identical said sub-memory array are connected with an identical said word voltage.