Reducing data transition rates between analog and digital chips

A system for reducing a transition rate in transmitting data between digital and analog chips, the system comprising:

• an interface configured to:
• receive data from a data source on a first chip;
• map the data to a transition binary code, the transition binary code comprising a series of 0s and 1s, wherein a number of transitions from 0 to 1 and from 1 to 0 depends on a probability of a value of the data;
• apply an XOR filter to every other bit of the data while mapping the data to the transition binary code;
• and
• transmit the transition binary code to a second chip, the second chip being configured to apply an XOR filter to every other bit of the transition binary code after receiving the transition binary code from the interface.

A non-transitory processor-readable medium having embodied thereon a program being executable by at least one processor to perform a method for reducing a transition rate in transmitting data between digital and analog chips, the method comprising:

• receiving data from a data source on a first chip;
• mapping the data to a transition binary code, the transition binary code comprising a series of 0s and 1s, wherein a number of transitions from 0 to 1 and from 1 to 0 depends on a probability of a value of the data;
• applying an XOR filter to every other bit of the data while mapping the data to the transition binary codes;
• transmitting the transition binary code to a second chip;
• and
• applying an XOR filter to every other bit of the transition binary code after transmitting to the second chip.