Vertical TFT with tunnel barrier
AssigneeSanDisk 3D LLC
InventorsMing-Che Wu, Peter Rabkin, Tim Chen
Life of this patent
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Abstract
A vertically oriented thin film transistor (TFT) having a tunnel barrier is disclosed. The tunnel barrier may be formed from a dielectric such as silicon oxide or hafnium oxide. The vertically oriented TFT selection device with tunnel barrier may serve as a selection device in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a global bit line to/from a vertical bit line in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a source line to/from a channel of a vertical NAND string in a 3D memory array. A vertical TFT with tunnel barrier has a high breakdown voltage, low leakage current, and high on current. The tunnel barrier can be at the top junction or bottom junction of the TFT.
Claims20
A semiconductor device comprising:
- a lower conductor;
- an upper conductor above the lower conductor;
- and
- a vertical thin film transistor (TFT) between the lower conductor and the upper conductor, the vertical TFT comprising:
- a first source/drain region having a first conductivity, wherein the first source/drain region is in electrical contact with the lower conductor;
- a second source/drain region having the first conductivity, wherein the second source/drain region is in electrical contact with the upper conductor;
- a channel region between the first source/drain region and the second source/drain region, the channel region having a second conductivity;
- and
- a tunnel barrier that comprises an insulator between either first source/drain region and the channel region or the second source/drain region and the channel region.
A method for forming a semiconductor device, the method comprising:
- forming a lower conductor;
- forming a vertically oriented thin film transistor (TFT), comprising:
- forming a first semiconductor region having a first conductivity over and in electrical contact with the lower conductor;
- forming a tunnel barrier over the first semiconductor region, wherein the tunnel barrier comprises an insulator;
- forming a second semiconductor region having a second conductivity over the tunnel barrier;
- forming a third semiconductor region having the first conductivity over the second semiconductor region;
- and
- forming a gate adjacent to the second semiconductor region;
- and
- forming an upper conductor over and in electrical contact with the third semiconductor region.
A non-volatile storage system, comprising:
- a substrate;
- a three dimensional memory array of memory cells positioned above the substrate;
- a plurality of word lines coupled to the memory cells;
- a plurality of global bit lines;
- a plurality of vertically oriented bit lines coupled to the memory cells;
- and
- a plurality of vertically oriented thin film transistor (TFT) select devices, the vertically oriented TFT select devices are coupled between the vertically oriented bit lines and the global bit lines;
- each of the vertically oriented TFT select devices comprising:
- a first semiconductor region having a first conductivity, wherein the first semiconductor region is in electrical contact with a first of the global bit lines;
- a second semiconductor region having a second conductivity;
- a third semiconductor region having the first conductivity, wherein the third semiconductor region is in electrical contact with a first of the vertical bit lines, wherein the second semiconductor region is between the first semiconductor region and the second semiconductor region;
- a tunnel barrier between either the first semiconductor region and the second semiconductor region or between the third semiconductor region and the second semiconductor region, wherein the tunnel barrier comprises an insulator;
- and
- a gate adjacent to the second semiconductor region.
Dependencies are inferred from the claim text.