Multiplier operable to perform a variety of operations
AssigneeAltera Corporation
InventorsJames L. Ball, James R. Lawson
Life of this patent
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Abstract
Methods and apparatus are provided for implementing circuitry operable to perform barrel shifting, multiplication, and rotation operations in hard coded logic on a programmable chip. A hard coded multiplier is augmented using multiplexer circuitry, a logical operation, and a bypassable 2^N functional block. Based on control signals, the multiplexer circuitry can be used to select a rotation, multiplication, or barrel shifted output. Multiplexer control signals also provide sign information associated with operands passed to the multiplier. A single augmented multiplier can perform barrel shifting, rotation, or multiplication operations. Inputs of a multiplier can also be selectively grounded to allow the multiplier to perform logic operations.
Claims20
A programmable chip, comprising:
- a plurality of programmable logic elements;
- a hard-coded multiplier implemented using only AND gates and adders, the hard-coded multiplier configured to receive a first operand over a plurality of first operand input lines and a second operand over a plurality of second operand input lines and to provide a first output over a plurality of first output lines, wherein the plurality of first operand input lines and the plurality of second operand input lines are all inputs to the hard-coded multiplier,
- wherein a subset of the plurality of first operand input lines and a subset of the second plurality of input lines are grounded such that the hard-coded multiplier provides only two-input logic operations on a subset of the first plurality of output lines,
- wherein the hard-coded multiplier uses hard-coded logic to perform shifting, rotation, and multiplication operations in addition to hard-coded two-input logic operations, and wherein a subset of the plurality of output lines provides a plurality of XOR and non-XOR functions.
A system, comprising:
- a plurality of programmable logic elements;
- a hard-coded multiplier implemented using only AND gates and adders, the hard-coded multiplier configured to receive a first operand over a plurality of first operand input lines and a second operand over a plurality of second operand input lines and to provide a first output over a plurality of first output lines, wherein the plurality of first operand input lines and the plurality of second operand input lines are all inputs to the hard-coded multiplier,
- wherein a subset of the plurality of first operand input lines and a subset of the second plurality of input lines are grounded such that the hard-coded multiplier provides only two-input logic operations on a subset of the first plurality of output lines, and
- wherein the hard-coded multiplier uses hard-coded logic to perform shifting, rotation, and multiplication operations in addition to hard-coded two-input logic operations, and wherein a subset of the plurality of output lines provides a plurality of XOR and non-XOR functions.
A hard-coded multiplier comprising:
- means to receive a first operand over a plurality of first operand input lines and a second operand over a plurality of second operand input lines, wherein the plurality of first operand input lines and the plurality of second operand input lines are all inputs to the hard-coded multiplier;
- means to provide a first output over a plurality of first output lines, wherein a subset of the plurality of first operand input lines and a subset of the second plurality of input lines are grounded such that the hard-coded multiplier provides only two-input logic operations on a subset of the first plurality of output lines,
- wherein the hard-coded multiplier implemented using only AND gates and adders uses hard-coded logic to perform shifting, rotation, and multiplication operations in addition to hard-coded two-input logic operations, and wherein a subset of the plurality of first output lines provides a plurality of XOR and non-XOR functions.
Dependencies are inferred from the claim text.