Memory system having an unequal number of memory die on different control channels

A mass storage memory system, comprising:

• a plurality of flash memory die;
• a plurality of control channels, each of the plurality of control channels connected to a respective unique subset of the plurality of flash memory die, each of the plurality of control channels associated with a respective one of a plurality of flash memory controllers, and at least one of the plurality of control channels associated with a greater number of the plurality of flash memory die than another of the plurality of control channels, wherein a physical storage capacity of the at least one of the plurality of control channels is greater than a physical storage capacity of other of the plurality of control channels;
• wherein the plurality of flash memory die defines a total physical storage capacity for the mass storage memory system, and wherein a total logical storage capacity in the mass storage memory system is less than the total physical storage capacity;
• a logical block address (LBA) splitter configured to direct data received from the host system to each of the plurality of controllers based on a host logical address of the received data;
• and
• wherein the LBA splitter is configured to direct data such that a ratio of logical capacity to physical storage capacity in one of the plurality of control channels is equal to a ratio of logical storage capacity to physical storage capacity in each other of the plurality of control channels.

A method of managing a mass storage memory system having a processor and a plurality of flash memory die with a total physical storage capacity greater than a total logical storage capacity, where a first portion of the flash memory die is exclusively associated with a first control line and a first controller, a second portion of the flash memory die is exclusively associated with a second control line and a second controller, and a number of flash memory die and physical storage capacity in the first portion is greater than a number of flash memory die and physical storage capacity in the second portion, the method comprising the processor:

• receiving data associated with host logical block addresses from a host system;
• only directing received data associated with a first subset of a range of host logical block addresses to the first portion of the flash memory die and only directing received data associated with a second subset of the range of host logical block addresses to the second portion of the flash memory die;
• and
• wherein the processor maintains a ratio of a first total physical storage capacity to a first total logical storage capacity in the first portion of flash memory die equal to a ratio of a second total physical storage capacity to a second total logical storage capacity in the second portion of flash memory die.