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US 9,219,471 B2Granted
Circuitry for phase detector
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsung-Hsien Tsai, Chia-Chun Liao
Life of this patent
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Abstract
A circuit for a phase detector is provided. A first buffer of the circuit receives a data signal and generates a first modified data signal using the data signal. A notifier receives the data signal and determines whether a violation exists. A first multiplexer receives the first modified data signal and transmits a first multiplexer signal to a second multiplexer. The second multiplexer receives the first multiplexer data signal and the first modified data signal, and transmits a second multiplexer data signal to a flip-flop of the phase detector.
Claims20
A circuit for a phase detector, comprising:
- a first buffer configured to:
- receive a data signal;
- and
- apply a first delay to the data signal, using a first delay signal, to generate a first modified data signal;
- a notifier configured to:
- receive the data signal;
- and
- determine whether a violation exists in at least one of a setup timing margin or a hold timing margin;
- a first multiplexer configured to:
- receive the first modified data signal from the buffer at a 0-input of the first multiplexer;
- receive a random value at a 1-input of the first multiplexer;
- and
- transmit a first multiplexer data signal, comprising:
- responsive to the notifier determining that the violation exists in at least one of the setup timing margin or the hold timing margin, transmitting the random value as the first multiplexer data signal;
- and
- responsive to the notifier determining that the violation does not exist in at least one of the setup timing margin or the hold timing margin, transmitting the first modified data signal from the buffer as the first multiplexer data signal;
- and
- a second multiplexer configured to:
- receive the first modified data signal from the buffer at a 0-input of the second multiplexer;
- receive the first multiplexer data signal from the first multiplexer at a 1-input of the second multiplexer;
- receive a random value turn on control signal;
- and
- transmit a second multiplexer data signal to a D-pin of a flip-flop of the phase detector, comprising:
- responsive to the random value turn on control signal comprising 1, transmitting the first multiplexer data signal as the second multiplexer data signal;
- and
- responsive to the random value turn on control signal comprising 0, transmitting the first modified data signal from the buffer as the second multiplexer data signal.
23 more elements
A method, comprising:
- applying a first delay to a data signal, using a first delay signal, to generate a first modified data signal using a buffer;
- transmitting the first modified data signal from the buffer to a 0-input of a first multiplexer;
- receiving a random value at a 1-input of the first multiplexer;
- transmitting a first multiplexer data signal from the first multiplexer to a 1-input of a second multiplexer, comprising:
- responsive to determining that a violation exists in at least one of a setup timing margin or a hold timing margin, transmitting the random value as the first multiplexer data signal;
- and
- responsive to determining that the violation does not exist in at least one of the setup timing margin or the hold timing margin, transmitting the first modified data signal from the buffer as the first multiplexer data signal;
- receiving a random value turn on control signal at the second multiplexer;
- and
- transmitting a second multiplexer data signal from the second multiplexer to a D-pin of a flip-flop of a phase detector, comprising:
- responsive to the random value turn on control signal comprising 1, transmitting the first multiplexer data signal as the second multiplexer data signal;
- and
- responsive to the random value turn on control signal comprising 0, transmitting the first modified data signal from the buffer as the second multiplexer data signal.
10 more elements
A circuit for a phase detector, comprising:
- a first multiplexer configured to:
- receive a first modified data signal at a 0-input of the first multiplexer;
- receive a random value at a 1-input of the first multiplexer;
- and
- transmit a first multiplexer data signal, comprising:
- responsive determining that a violation exists in at least one of a setup timing margin or a hold timing margin, transmitting the random value as the first multiplexer data signal;
- and
- responsive to determining that the violation does not exist in at least one of the setup timing margin or the hold timing margin, transmitting the first modified data signal as the first multiplexer data signal;
- and
- a second multiplexer configured to:
- receive the first modified data signal at a 0-input of the second multiplexer;
- receive the first multiplexer data signal from the first multiplexer at a 1-input of the second multiplexer;
- receive a random value turn on control signal;
- and
- transmit a second multiplexer data signal to a flip-flop of the phase detector, comprising:
- responsive to the random value turn on control signal comprising 1, transmitting the first multiplexer data signal as the second multiplexer data signal;
- and
- responsive to the random value turn on control signal comprising 0, transmitting the first modified data signal as the second multiplexer data signal.
15 more elements
Dependencies are inferred from the claim text.