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US 9,218,974 B2Granted
Sidewall free CESL for enlarging ILD gap-fill window
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHan-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao
Life of this patent
Estimating the term…
Abstract
An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
Claims20
An integrated circuit structure comprising:
- a first conductive strip;
- a first spacer on a sidewall of the first conductive strip, the first spacer having a convex outermost sidewall;
- a second conductive strip;
- a second spacer on a sidewall of the second conductive strip;
- a gap between the first spacer and the second spacer;
- a top contact etch stop layer (CESL) directly over the first conductive strip;
- a bottom contact etch stop layer (CESL) in the gap and disconnected from the top CESL, wherein a portion of the convex outermost sidewall of the first spacer does not have a CESL formed thereon;
- and
- an inter-layer dielectric (ILD) in the gap, the ILD adjoining a sidewall of the bottom CESL between the first spacer and the bottom CESL.
6 more elements
An integrated circuit structure comprising:
- a first gate strip on a substrate;
- a first spacer on a sidewall of the first gate strip;
- a second gate strip on the substrate;
- a second spacer on a sidewall of the second gate strip;
- a source/drain structure adjacent the first gate strip and between the first spacer and the second spacer, the source/drain structure comprising a source/drain region;
- a first contact etch stop layer (CESL) directly over and contacting the source/drain structure;
- a second contact etch stop layer (CESL) directly over the first gate strip;
- and
- an inter-layer dielectric (ILD) over the first CESL, the ILD contacting the first spacer and a sidewall of the first CESL between the first CESL and the first spacer.
6 more elements
A device comprising:
- a first gate strip;
- a first gate spacer on a sidewall of the first gate strip;
- a second gate strip;
- a second gate spacer on a sidewall of the second gate strip;
- a contact etch stop layer (CESL) comprising a bottom portion lower than a top surface of the first gate spacer, the bottom portion disposed between the first gate spacer and the second gate spacer;
- and
- an inter-layer dielectric (ILD) over and contacting the CESL, the ILD contacting at least a portion of a sidewall of the first gate spacer and at least a portion of a sidewall of the second gate spacer, the ILD contacting a sidewall of the bottom portion of the CESL between the bottom portion and the first gate spacer.
4 more elements
Dependencies are inferred from the claim text.