Semiconductor package including stacked memory chips

A semiconductor package, comprising:

• a package substrate;
• a logic chip on the package substrate;
• first and second memory chips on the package substrate, the first and second memory chips electrically connected to the logic chip, the first and second memory chips spaced apart from the logic chip in a first direction, the first and second memory chips spaced apart from each other in a second direction crossing the first direction;
• third and fourth memory chips on the first and second semiconductor chips, respectively, the third and fourth memory chips electrically connected to the logic chip, a memory capacity of the first and second memory chips being twice a memory capacity of the third and fourth memory chips;
• and
• first and second jumper chips on the first and second semiconductor chips, respectively, the first and second jumper chips spaced apart from the third and fourth memory chips, respectively, in the first direction.

A semiconductor package, comprising:

• a first substrate;
• a logic chip on the first substrate, the logic chip including a first number of data pads and a second number of communication pads;
• a second substrate on the logic chip;
• first memory chips spaced apart from each other in a first direction on the second substrate, the first memory chips including a first quantity of first memory data pads and a second quantity of first memory command/address pads, which are electrically connected to the logic chip;
• second memory chips on the first memory chips, the second memory chips including a third of quantity of second memory data pads and a fourth quantity of second memory command/address pads, which are electrically connected to the logic chip;
• and
• jumper chips on the first memory chips, the jumper chips spaced apart from the second memory chips in a second direction crossing the first direction, the jumper chips including a fifth quantity of first wire bond pads and second wire bond pads, respectively, which are electrically connected to the logic chip.