Data processor for processing a decorated storage notify

A processor comprising:

• an execution unit;
• and
• an interface unit for coupling to a split-transaction system interconnect that utilizes a split-transaction protocol for transferring of operands using an address bus and a data bus;
• wherein the processor is configured to:
• initiate first and second transactions of a first type of interconnect transaction that is a split-transaction to a target device via the split-transaction system interconnect, the first type of interconnect transaction including an address phase using the address bus and a data phase using the data bus;
• and
• initiate an address-only transaction between the first and second transactions to a target device via the split-transaction system interconnect, the address-only transaction including an address phase using the address bus and no data phase thereby not using the data bus, the address-only transaction providing a decoration value indicated by a notify instruction comprising a read-modify-write operation to be performed by the target device that does not use the data bus so that the second transaction can use the data bus during a time the address-only transaction would have used the data bus if the address-only transaction had been the first type of interconnect transaction with an address phase and a data phase.

A method of operating a data processing system including a split-transaction system interconnect that utilizes a split-transaction protocol for transferring operands, the method comprising:

• receiving by a target device a first transaction of a first type of split-transaction initiated by a processor, the first type of split-transaction including address information carried by address signals over an address bus of the split-transaction system interconnect and data information carried by a data signals over a data bus of the split-transaction system interconnect, the first type of split-transaction including an indication of a device operation;
• performing the device operation by the target device in response to the first type of split-transaction;
• receiving by the target device over the split-transaction system interconnect an address-only transaction initiated by the processor, the address-only transaction including address information carried by address signals over the address bus of the split-transaction system interconnect and no data information carried over the data bus of the split-transaction system interconnect, the address-only transaction including a decoration value indicated by a notify instruction comprising a read-modify-write operation and the target device detects the decoration value and performs the read-modify-write operation using an address phase using the address bus and no subsequent data phase on the split-transaction system interconnect and thereby does not use the data bus;
• performing the read-modify-write operation of a storage location of the target device in response to the address-only transaction in response to only the address phase of the address-only transaction without a subsequent data phase occurring on the split-transaction system interconnect;
• and
• receiving by the target device a second transaction of the first type of split-transaction initiated by the processor using the address bus and the data bus, wherein the using the data bus is during a time the address-only transaction would have used the data bus if the address-only transaction had been the first type of split-transaction.

A method of operating a data processing system including a processor, a split-transaction system interconnect that utilizes a split-transaction protocol for transferring operands, and an intelligent memory, wherein the processor and the intelligent memory are operably coupled to the split-transaction system interconnect, the method comprising:

• performing by the intelligent memory, a first memory operation in response to a first split-transaction on the split-transaction system interconnect from the processor, wherein the first split-transaction includes an address phase using an address bus and a data phase using a data bus;
• and
• performing by the intelligent memory, a second memory operation in response to an address-only transaction on the split-transaction system interconnect from the processor, wherein the address-only transaction includes an address phase using the address bus and no subsequent data phase for the address-only transaction on the split-transaction system interconnect thereby not using the address bus;
• wherein the performing the second memory operation by the intelligent memory includes performing a read-modify-write operation of a storage location of the intelligent memory in response to only the address phase of the address-only transaction without a subsequent data phase occurring on the split-transaction system interconnect for the second transaction;
• wherein the address phase of the address-only transaction includes a decoration value, and performing the second memory operation includes performing a decoration operation specified by the decoration value;
• performing by the intelligent memory, a third memory operation in response to a third split-transaction received, immediately after the address-only transaction was received, on the split-transaction system interconnect from the processor, wherein the third split-transaction includes an address phase using the address bus and a data phase using the data bus, wherein the using the data bus occurs during a time the second memory operation would have used the data bus if the second memory operation had been a split-transaction with an address phase and a data phase.