Semiconductor memory device and semiconductor memory system including the same
AssigneeSK hynix Inc.
InventorMi-Hyun Hwang
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a plurality of normal word lines and a plurality of redundancy word lines which are disposed adjacent to the normal word lines, a detection block suitable for detecting a first word line whose active history satisfies a predetermined condition and a second word line adjacent to the first word line as a target word line and a target neighboring word line, among the normal word lines and the redundancy word lines, and a control block suitable for sequentially refreshing the normal word lines and the redundancy word lines whenever a refresh command is applied, and additionally refreshing the target word line, the target neighboring word line and a normal word line adjacent to the redundancy word lines among the normal word lines.
Claims19
A semiconductor memory device, comprising:
- a plurality of normal word lines and a plurality of redundancy word lines which are disposed adjacent to the normal word lines;
- a detection block suitable for detecting a first word line whose active history satisfies a predetermined condition and a second word line adjacent to the first word line as a target word line and a target neighboring word line, among the normal word lines and the redundancy word lines;
- and
- a control block suitable for sequentially refreshing the normal word lines and the redundancy word lines whenever a refresh command is applied, and additionally refreshing the target word line, the target neighboring word line and a normal word line adjacent to the redundancy word lines among the normal word lines.
The semiconductor memory device of claim wherein the control block performs:
- a first refresh operation to sequentially refresh the normal word lines whenever the refresh command is applied;
- a second refresh operation to sequentially refresh the target word line and the target neighboring word line while stopping the first refresh operation whenever the refresh command is applied at an Mth time;
- a third refresh operation to sequentially refresh the redundancy word lines while stopping the first refresh operation whenever the refresh command is applied at an (M+N)th time;
- and
- a fourth refresh operation to refresh the normal word line adjacent to the redundancy word lines among the normal word fines in response to the refresh command applied after the first to third refresh operations are performed,
- wherein the M and N include a natural number greater than 1.
A semiconductor system, comprising:
- a semiconductor memory device including a plurality of normal word lines and a plurality of redundancy word lines which are disposed adjacent to the normal word lines, and suitable for sequentially refreshing the normal v cord lines and the redundancy word lines whenever a refresh command is applied, and additionally refreshing a target word line, a target neighboring word line adjacent to the target word line and a normal word line adjacent to the redundancy word lines among the normal word lines and the redundancy word lines;
- and
- a semiconductor controller suitable for detecting a word line whose active history satisfies a predetermined condition among the normal word lines and the redundancy word lines as the target word line, and transmitting a detection result to the semiconductor memory device.
Dependencies are inferred from the claim text.