Semiconductor memory device having an electrically floating body transistor
AssigneeZeno Semiconductor, Inc.
InventorsYuniarto Widjaja, Zvi Or-Bach
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Abstract
A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.
Claims20
A semiconductor memory cell formed in a semiconductor, the semiconductor memory cell comprising:
- a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type;
- a buried region located within the semiconductor memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type,
- wherein the floating body region is bounded on the sides by at least a first insulating region having a first thickness and a second insulating region having a second thickness, wherein the second thickness is greater than the first thickness;
- and
- a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer.
An array of memory cells formed in a semiconductor, the array comprising:
- a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein the rows of memory cells define a first direction and the columns of memory cells define a second direction, and each of said memory cells comprising:
- a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;
- a buried region located beneath the surface of the memory cell, the buried region having a second conductivity type;
- and
- a gate region above the floating body region, where the gate region overlays two floating body regions in the first direction.
An array of memory cells formed in a semiconductor, the array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and a plurality of columns wherein the rows of memory cells define a first direction and the columns of memory cells define a second direction, and each of said memory cells comprising:
- a bipolar device having a floating base region, a first region, a second region, and a gate region wherein:
- a state of said semiconductor memory cell is stored in said floating base region;
- said first region is located at the surface of said floating base region;
- said second region is located below said floating base region,
- said second region is commonly connected to at least two of said semiconductor memory cells in said matrix;
- and
- said gate region overlays two of said semiconductor memory cells along the column direction.
Dependencies are inferred from the claim text.