Digital signal processing blocks with embedded arithmetic circuits

A method for operating a given specialized processing block in a plurality of specialized processing blocks, wherein the given specialized processing block includes a multiplier stage, an adder stage, a multiplexer and configurable interconnect circuitry, the method comprising:

• with the configurable interconnect circuitry, routing signals from the adder stage to the multiplexer;
• with the configurable interconnect circuitry, bypassing the adder stage by routing signals from the multiplier stage to the multiplexer;
• selecting between the signals from the multiplier stage and the signals from the adder stage using the multiplexer;
• and
• with the multiplexer that has a multiplexer output, routing the selected signals to the multiplexer output that is directly coupled to another one of the plurality of specialized processing blocks.

A method for operating first and second specialized processing blocks, wherein each of the first and second specialized processing blocks includes an arithmetic operator stage and configurable interconnect circuitry, the method comprising:

• receiving a first signal at an input of the first specialized processing block;
• with the configurable interconnect circuitry of the first specialized processing block, routing the first signal from the input to a first register of the first specialized processing block;
• with the configurable interconnect circuitry of the first specialized processing block, bypassing the arithmetic operator stage of the first specialized processing block by routing the first signal from the first register through a multiplexer to a second register of the first specialized processing block;
• and
• with the configurable interconnect circuitry of the first specialized processing block, bypassing the arithmetic operator stage of the first specialized processing block by routing the first signal from the second register to an output of the first specialized processing block, wherein the output is coupled to an input of the second specialized processing block.