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US 9,206,520 B2Granted
Inhibiting background plating
AssigneeRohm and Haas Electronic Materials LLC
InventorsRobert K. Barr, Hua Dong, Thomas C. Sutter
Life of this patent
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Abstract
Methods include selectively depositing a phase change resist having high light transmittance onto a dielectric to form a pattern, etching away portions of the dielectric not covered by the resist and depositing a metal seed layer on the etched portions of the dielectric. A metal layer is then deposited on the metal seed layer by light induced plating.
Claims10
A method comprising:
- a) providing a doped semiconductor comprising an n doped front side and a p doped back side, and a dielectric layer covering the n doped front side of the doped semiconductor;
- b) selectively depositing a phase change resist having a light transmission of 30% or greater onto the dielectric layer to form a pattern on the dielectric layer;
- c) etching away sections of the dielectric layer not covered with the phase change resist to expose sections of the n doped front side of the doped semiconductor;
- d) depositing a metal seed layer on the exposed sections of the n doped front side of the doped semiconductor;
- and
- e) depositing a metal layer on the metal seed layer by light induced plating.
3 more elements
Dependencies are inferred from the claim text.