Quadrature lattice matching network
AssigneeTriQuint Semiconductor, Inc.
InventorPeter V. Wright
Life of this patent
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Abstract
Embodiments include but are not limited to apparatuses and systems including a quadrature lattice matching network including first path having a series inductor and a shunt inductor, and a second path having a series capacitor and a shunt capacitor. Other embodiments may be described and claimed.
Claims25
An apparatus comprising:
- a first power amplifier having a first output for providing a first signal;
- a second power amplifier having a second output for providing a second signal;
- and
- a quadrature lattice matching network including a first path coupled with the first output of the first power amplifier and having a series inductor and a shunt inductor that substantially provide a positive forty-five degree phase shift to the first signal, and a second path coupled with the second output of the second power amplifier and having a series capacitor and a shunt capacitor that substantially provide a negative forty-five degree phase shift to the second signal,
- wherein the first power amplifier is configured to operate with a phase difference of approximately ninety degrees with respect to the second power amplifier.
An apparatus comprising:
- a quadrature lattice matching network including;
- a first path having a series inductor and a shunt inductor that substantially provide a positive forty-five degree phase shift to a first signal;
- a second path having a series capacitor and a shunt capacitor that substantially provide a negative forty-five degree phase shift to a second signal;
- and
- an output node to receive a first waveform from the first path and a second waveform from the second path and to combine the first and second waveforms;
- a first power amplifier having a first output coupled with the first path of the quadrature lattice matching network, wherein the first signal is provided through the first output;
- and
- a second power amplifier having a second output coupled with the second path of the quadrature lattice matching network, wherein the second signal is provided through the second output.
The apparatus of 20, further comprising a second switch selectively coupling a second node, which is between the series capacitor and the shunt capacitor, with the output node of the quadrature lattice matching network.
The apparatus of 20, further comprising a second switch selectively coupling the first node with a second node, which is between the series capacitor and the shunt capacitor.
Dependencies are inferred from the claim text.