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US 9,202,871 B2Granted
JFET devices with increased barrier height and methods of making same
AssigneeMicron Technology, Inc.
InventorChandra Mouli
Life of this patent
Estimating the term…
Abstract
Devices for providing transistors with improved operating characteristics are provided. In one example, a system includes a processor and a memory device. A transistor of the processor or the memory device includes a channel in a semiconductor substrate that is undoped or intrinsic. A metal gate is disposed directly on top of the channel, and the bandgap of the semiconductor substrate and the work function of the metal form a Schottky barrier.
Claims20
A memory device, comprising:
- a semiconductor substrate comprising a source region and a drain region;
- a charge storage device coupled to either the source region or the drain region;
- a channel formed in the semiconductor substrate between the source region and the drain region, the channel configured to pass current between the source region and the drain region;
- and
- a gate comprising a metal formed directly on a top surface of the semiconductor substrate over the channel;
- wherein a Schottky barrier is formed between the gate and the channel;
- and
- wherein:
- the channel is n-type and the metal comprises palladium, nickel, tungsten, or molybdenum, or a silicide of palladium, nickel, tungsten, or molybdenum;
- or
- the channel is p-type and the metal comprises magnesium, tantalum, hafnium, or a silicide of magnesium, tantalum, or hafnium;
- or
- the channel is undoped or intrinsic and the metal comprises palladium, nickel, magnesium, tantalum, hafnium, tungsten, or molybdenum, or a silicide of any of these.
10 more elements
A system comprising:
- a processor configured to execute instructions;
- and
- a memory device configured to store at least some of the instructions executed by the processor;
- wherein the processor or the memory device, or both, comprise a transistor comprising:
- a channel in a semiconductor substrate, wherein the channel is undoped or intrinsic;
- and
- a metal gate directly on top of the channel;
- wherein the bandgap of the semiconductor substrate and the work function of the metal form a Schottky barrier.
5 more elements
A memory device comprising:
- a semiconductor substrate comprising a source region and a drain region;
- a channel formed in the semiconductor substrate between the source region and the drain region, the channel configured to pass current between the source region and the drain region;
- and
- a gate formed directly on a top surface of the semiconductor substrate over the channel, the gate comprising a gate material;
- wherein a bandgap of the gate material is higher than a bandgap of the channel material;
- and
- wherein:
- the channel is n-type and the gate material comprises palladium, nickel, tungsten, or molybdenum, or a silicide of palladium, nickel, tungsten, or molybdenum;
- or
- the channel is p-type and the gate material comprises magnesium, tantalum, hafnium, or a silicide of magnesium, tantalum, or hafnium;
- or
- the channel is undoped or intrinsic and the gate material comprises palladium, nickel, magnesium, tantalum, hafnium, tungsten, or molybdenum, or a silicide of any of these.
9 more elements
A system comprising:
- a processor configured to execute instructions;
- and
- a memory device configured to store at least some of the instructions executed by the processor;
- wherein the processor or the memory device, or both, comprise a transistor comprising:
- a channel in a semiconductor substrate having a first dopant;
- a second, underlying semiconductor substrate beneath the channel, the second, underlying semiconductor substrate having a second dopant;
- a gate directly on top of the channel;
- and
- a terminal directly coupled between the second, underlying semiconductor substrate and the gate to electrically couple the second, underlying doped layer to the gate.
6 more elements
Dependencies are inferred from the claim text.