Methods of fabricating fan-out wafer level packages and packages formed by the methods

A fan-out wafer level package, comprising:

• at least two semiconductor chips;
• an insulating layer covering portions of a first semiconductor chip of the at least two semiconductor chips;
• a mold layer covering portions of a second semiconductor chip of the at least two semiconductor chips;
• a redistribution line pattern in the insulating layer;
• and
• an external terminal on an opposite side of the insulating layer from the at least two semiconductor chips;
• wherein the first semiconductor chip is stacked relative to the second semiconductor chip,
• wherein the redistribution line pattern is electrically connected to the at least two semiconductor chips, and
• wherein the external terminal is electrically connected to the redistribution line pattern.

A fan-out wafer level package, comprising:

• at least three semiconductor chips;
• an insulating layer covering portions of first semiconductor chips of the at least three semiconductor chips;
• a mold layer covering portions of a second semiconductor chip of the at least three semiconductor chips;
• a redistribution line pattern in the insulating layer;
• and
• an external terminal on an opposite side of the insulating layer from the at least three semiconductor chips;
• wherein the first semiconductor chips are stacked relative to the second semiconductor chip,
• wherein the redistribution line pattern is electrically connected to the at least three semiconductor chips, and
• wherein the external terminal is electrically connected to the redistribution line pattern.