Method and circuit for noise shaping SAR analog-to-digital converter
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorMartin Kinyua
Life of this patent
Estimating the term…
Abstract
An analog-to-digital conversion system includes a track-and-hold unit configured to output an input value; a digital-to-analog (D/A) conversion unit configured to generate a feedback value; a coupling unit configured to generate an error signal value based on the input signal and the feedback value; a loop filter configured to generated a filtered error signal value; a comparison unit configured to generate a comparison result based on the input value minus the summation of the feedback value and the filtered error signal value; and a control unit. The control unit is configured to, during a sampling cycle, set an N-bit logical value accordingly to N comparison results; and to cause the coupling unit to generate the error signal value. N is a positive integer.
Claims20
An analog-to-digital (A/D) conversion system, comprising:
- a track-and-hold unit configured to output an input value based on an input signal;
- a digital-to-analog (D/A) conversion unit configured to generate a feedback value based on an N-bit logical value, N being a positive integer;
- a coupling unit configured to generate an error signal value based on the input signal and the feedback value;
- a hardware loop filter configured to generated a filtered error signal value based on the error signal value;
- a comparison unit configured to generate a comparison result based on a polarity of a combined value, the combined value being based on the input value minus the summation of the feedback value and the filtered error signal value;
- and
- a control unit configured to, during a sampling cycle,
- set the N-bit logical value according to N comparison results from the comparison unit;
- and
- cause the coupling unit to generate the error signal value after receipt of the N comparison results.
An analog-to-digital (A/D) conversion circuit, comprising:
- a loop filter configured to generated a filtered error signal voltage level based on an error signal voltage level;
- and
- an N-bit successive approximation register (SAR) analog-to-digital converter (ADC) configured to receive an input voltage, N being a positive integer, and the SAR ADC comprising:
- a comparator configured to generate a comparison result based on an input voltage level, an N-bit logical value, and the filtered error signal voltage level;
- and
- an SAR controller configured to:
- cause an input voltage signal of the comparator to be set based on the N-bit logical value;
- set the N-bit logical value based on the comparison result;
- and
- cause the SAR ADC to generate another error signal voltage level after the SAR controller receives N comparison results from the comparator during a sampling cycle.
A method of operating an analog-to-digital (A/D) conversion circuit, comprising:
- during a sampling cycle:
- generating an N-bit logical value based on a filtered error signal voltage and an input voltage by operating a successive approximation register (SAR) analog-to-digital converter (ADC), N being a positive integer;
- and
- generating an error signal voltage based on the N-bit logical value and the input voltage;
- and
- during the sampling cycle or a next sampling cycle:
- generating, by a loop filter, another filtered error signal voltage based on the error signal voltage of the sampling cycle, the another filtered error signal voltage being usable as a filtered error signal voltage of the next sampling cycle.
Dependencies are inferred from the claim text.