Data bus efficiency via cache line usurpation
AssigneeEmulex Corporation
InventorsSteven Gerard LeMire, Vuong Cao Nguyen
Life of this patent
Estimating the term…
Abstract
Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.
Claims20
A method for allocating cache memory, comprising:
- determining whether a cache memory location is required for an operating system command;
- and
- if the cache memory location is required for an operating system command:
- allocating the cache memory location,
- linking the main memory location to the cache memory location, and
- bypassing reading the main memory location into the cache memory location.
A method for allocating cache memory, comprising:
- determining whether a cache memory location is required for an operating system command;
- and
- if the cache memory location is required for an operating system command:
- allocating the cache memory location, and
- suppressing reading the main memory location into the cache memory location.
A device comprising:
- a cache memory comprising one or more cache memory locations;
- a connection to a main memory, the main memory comprising one or more main memory locations;
- and
- a control unit coupled to the cache memory, wherein the control unit is operable to:
- determine whether the cache memory location is required for an operating system command, and
- link the main memory location to the cache memory location and bypass reading data from the main memory location to the cache memory location, if the cache memory location is required for an operating system command.
Dependencies are inferred from the claim text.