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US 9,191,529 B2Granted
Quad-core camera processor
AssigneeGoogle Inc.
InventorKia Silverbrook
Life of this patent
Estimating the term…
Abstract
A quad-core processor for a camera with a CMOS image sensor. The quad-core processor has an image sensor interface for receiving data from the CMOS image sensor and four processing units configured for operating in parallel to process the data from the image sensor interface. The four processing units and the image sensor interface are integrated onto a single chip.
Claims20
A processor for a device that includes a camera, the processor comprising:
- an image sensor interface for receiving data from an image sensor associated with the camera;
- multiple processing units configured for operating in parallel to process the data from the image sensor interface, wherein a data transfer channel is directly coupled to each of the multiple processing units for the transmission of data, such data transfer channel being separate and independent from a dedicated processing channel connected between the multiple processing units that provides a pathway for communication among the multiple processors during parallel processing;
- and
- a plurality of interfaces for transmitting data processed by the multiple processing units to functional components within the device through such data transfer channel, wherein each processing unit of the multiple processing units includes at least one address generator for addressing processed data for transmission to the functional components through such data transfer channel;
- wherein the multiple processing units, the plurality of interfaces, and the image sensor interface are integrated onto a single chip.
2 more elements
A hand held imaging device, comprising:
- an image sensor;
- and
- a processor, comprising:
- an image sensor interface for receiving data from the image sensor,
- multiple processing units configured for operating in parallel to process the data from the image sensor interface, wherein a data transfer channel is directly coupled to each of the multiple processing units for the transmission of data, such data transfer channel being separate and independent from a dedicated processing channel connected between the multiple processing units that provides a pathway for communication among the multiple processors during parallel processing, and
- a plurality of interfaces for transmitting data processed by the multiple processing units to functional components through such data transfer channel within the device, wherein each processing unit of the multiple processing units includes at least one address generator for addressing processed data for transmission to the functional components through such data transfer channel,
- wherein the multiple processing units, the plurality of interfaces, and the image sensor interface are integrated onto a single chip.
4 more elements
Dependencies are inferred from the claim text.