Digital filter
AssigneeIntel Mobile Communications GmbH
InventorAndreas Menkhoff
Life of this patent
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Abstract
A first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.
Claims20
A digital filter, comprising:
- a first stage configured to operate with a first computational complexity and a first frequency clock;
- and
- a second stage configured to operate with a second computational complexity and a second frequency clock,
- wherein:
- the digital filter is configured to transmit at least two signals between the first stage and the second stage,
- the second frequency clock is of a greater frequency than the first frequency clock,
- the first computational complexity is greater than the second computational complexity, and
- the ratio of the first frequency clock to the second frequency clock is fractional.
A method, comprising:
- operating a first stage of a digital filter with a first computational complexity and a first frequency clock;
- operating a second stage of the digital filter with a second computational complexity and a second frequency clock;
- and
- transmitting at least two signals between the first stage and the second stage, wherein:
- the second frequency clock is of a greater frequency than the first frequency clock,
- the first computational complexity is greater than the second computational complexity, and
- the ratio of the first frequency clock to the second frequency clock is fractional.
A digital filter, comprising:
- a first stage configured to operate with a first frequency clock;
- and
- a second stage configured to operate with a second frequency clock, wherein:
- the digital filter is configured to transmit at least two signals between the first stage and the second stage,
- the second frequency clock is of a greater frequency than the first frequency clock,
- a power consumption of the first stage during a clock cycle of the first frequency clock is greater than a power consumption of the second stage during a clock cycle of the second frequency clock, and
- the ratio of the first frequency clock to the second frequency clock is fractional.
A method, comprising:
- operating a first stage of a digital filter with a first frequency clock;
- operating a second stage of a digital filter with a second frequency clock;
- and
- transmitting at least two signals between the first stage and the second stage, wherein:
- the second frequency clock is of a greater frequency than the first frequency clock,
- a power consumption of the first stage during a clock cycle of the first frequency clock is greater than a power consumption of the second stage during a clock cycle of the second frequency clock, and
- the ratio of the first frequency clock to the second frequency clock is fractional.
Dependencies are inferred from the claim text.