Digitally-programmable gain amplifier with direct-charge transfer and offset cancellation

A Programmable-Gain Amplifier (PGA) comprising:

• an amplifier having a first input and a second input and an output;
• a sampled input;
• a sampling capacitor connected between a direct-charge transfer node and a summing node;
• a primary sampling switch that connects the sampled input to the direct-charge transfer node in response to a first clock;
• a variable capacitor connected between a first sampling node and the summing node, wherein a capacitance value of the variable capacitor is determined by a digital input having a multi-bit digital value;
• a first sampling switch that connects the sampled input to the first sampling node in response to the first clock;
• a first grounding switch that connects the first sampling node to a virtual ground in response to a second clock;
• a summing grounding switch that connects the summing node to the virtual ground in response to the first clock;
• a connecting switch that connects the summing node to a feedback node in response to the second clock;
• a feedback capacitor connected between the feedback node and the output of the amplifier;
• and
• a direct-charge transfer switch that connects the direct-charge transfer node to the output of the amplifier in response to the second clock;
• wherein the feedback node drives the first input of the amplifier.

A front-end circuit comprising:

• amplifier means for generating an output in response to a difference between a first input and a second input;
• sampling switch means for connecting a sampled input to a direct-charge node in response to a first clock;
• sampling capacitor means for storing a charge between the direct-charge node and a summing node;
• variable capacitor means having a plurality of sub-capacitors that are enabled by a multi-bit digital value to set a gain of the front-end circuit;
• a plurality of first switch means for connecting the sampled input to first plates of enabled sub-capacitors in the plurality of sub-capacitors in response to the first clock;
• a plurality of first grounding switch means for connecting a virtual ground to the first plates of enabled sub-capacitors in the plurality of sub-capacitors in response to a second clock;
• wherein second plates of enabled sub-capacitors in the plurality of sub-capacitors are connected to the summing node;
• summing grounding switch means for connecting the summing node to the virtual ground in response to the first clock;
• connecting switch means for connecting the summing node to a feedback node in response to the second clock;
• feedback capacitor means for storing charge between the feedback node and the output of the amplifier means;
• direct-charge transfer switch means for connecting the direct-charge node to the output of the amplifier means in response to the second clock;
• double-sampling capacitor means for storing charge between the summing node and the first input of the amplifier means;
• and
• offset switch means for connecting the feedback node to the first input of the amplifier means in response to the first clock.