Folded FIFO memory generator
AssigneeNVIDIA Corporation
InventorRobert A. Alfieri
Life of this patent
Estimating the term…
Abstract
Synthesizable code representing first-in-first out (FIFO) memories may be used to produce FIFO memories in a hardware element or system. To more efficiently use a memory element that stores the data in a FIFO, a code generator may generate a wrapper that enables the FIFO to use a memory element with different dimension (i.e., depth and width) than the FIFO's dimensions. For example, the wrapper enables a 128 deep, 1 bit wide FIFO to store data in a memory element with 16 rows that store 8 bits each. To any system communicating with the FIFO, the FIFO behaves like a 128×1 FIFO even though the FIFO is implemented using a 16×8 memory element. To do so, the code generator may generate a wrapper which enables the folded memory element to behave like a memory element that was not folded.
Claims22
A method, comprising:
- receiving a request to store a first data portion in a first-in first-out (FIFO) memory, wherein the FIFO memory includes a memory element comprising a plurality of rows and has depth and width dimensions that differ from depth and width dimensions of the FIFO memory, and a buffer that is sized to store a single row of the memory element;
- storing the first data portion in the buffer in the FIFO memory;
- receiving a request to store a second data portion in the FIFO memory;
- determining that storing the second data portion in the buffer would exceed a capacity of the buffer;
- and
- transferring the contents of the buffer into a single row of the memory element in the FIFO memory, wherein each row in the memory element is sized to store multiple data portions.
A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to:
- receive a request to store a first data portion in a first-in first-out (FIFO) memory, wherein the FIFO memory includes a memory element comprising a plurality of rows and has depth and width dimensions that differ from depth and width dimensions of the FIFO memory, and a buffer that is sized to store a single row of the memory element;
- store the first data portion in the buffer in the FIFO memory;
- receive a request to store a second data portion in the FIFO memory;
- determine that storing the second data portion in the buffer would exceed a capacity of the buffer;
- and
- transfer the contents of the buffer into a single row of the memory element in the FIFO memory, wherein each row in the memory element is sized to store multiple data portions.
A FIFO memory, comprising:
- a memory element comprising a plurality of rows and coupled to a buffer, wherein each row in the memory element is sized to store multiple data portions, and wherein the memory element has depth and width dimensions that differ from depth and width dimensions of the FIFO;
- the buffer for storing a plurality of data portions associated with write requests received by the FIFO memory, wherein the buffer is sized to store a single row of the memory element;
- and
- routing logic configured to determine that storing a next data portion in the buffer would exceed a capacity of the buffer and transfer the contents of the buffer into a single row of the memory element.
Dependencies are inferred from the claim text.