Enhanced I/O performance in a multi-processor system via interrupt affinity schemes
AssigneeEmulex Corporation
InventorsQiang Liu, Allen Russell Andrews, David Bradley Baldwin
Life of this patent
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Abstract
Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.
Claims20
A system for controlling interrupt processing, the system comprising:
- an adapter operable to generate an interrupt, wherein the interrupt is communicated over a channel selected from a plurality of channels and the interrupt is processed by a processor selected from a plurality of processors,
- wherein the processor is selected according to a first mapping and the channel is selected according to a second mapping,
- wherein the first mapping comprises an association between the processor and the interrupt, wherein the interrupt is mapped to the processor that requested an operation triggering the interrupt, the first mapping having a first group of assignments between one or more processors of the plurality of processors and a plurality of respective interrupt identifiers, and
- wherein the second mapping comprises an association between the interrupt and the channel and the second mapping is adaptable based on a usage of one or more processors of the plurality of processors as assigned in the first mapping, the second mapping having a second group of assignments between the plurality of respective interrupt identifiers and one or more channels of the plurality of channels.
An adapter for controlling interrupt processing, the adapter comprising:
- a worker kernel thread operable to handle an interrupt;
- and
- an interrupt thread operable to wake up the worker kernel thread,
- wherein the interrupt is communicated over a channel selected from a plurality of channels and the interrupt is processed by a processor selected from a plurality of processors,
- wherein the processor is selected according to a first mapping and a second mapping, the first mapping having a first group of assignments between one or more processors of the plurality of processors and a plurality of respective interrupt identifiers, the second mapping having a second group of assignments between the plurality of respective interrupt identifiers and one or more channels of the plurality of channels, the second mapping being adaptable based on a usage of the first mapping.
A method for controlling interrupt processing, the method comprising:
- generating an interrupt;
- selecting a processor from a plurality of processors according to the interrupt and a first mapping, the first mapping having a first group of assignments between one or more processors of a plurality of processors and a plurality of respective interrupt identifiers;
- communicating the interrupt over a selected channel according to a second mapping, the second mapping having a second group of assignments between the plurality of respective interrupt identifiers and one or more channels of a plurality of channels, the second mapping being adaptable based on a usage of the first mapping;
- waking up a worker kernel thread;
- and
- handling the interrupt by the worker kernel thread associated with the processor.
Dependencies are inferred from the claim text.