Fast switching hybrid video decoder

An apparatus comprising:

• a hybrid decoder including a software decoder and a hardware decoder;
• a memory having a first and second buffer;
• a processor configured to:
• receive a video bit stream;
• analyze the video bit stream to determine whether or not the video bit stream can be decoded by the hardware decoder;
• responsive to determining that the video bit stream can be decoded by the hardware decoder while routing the video bit stream to the software decoder, switch decoding from the software decoder to the hardware decoder by which the processor is configured to:
• route the video bit stream from the software decoder to the hardware decoder;
• store the video bit stream in the first buffer;
• decode the video bit stream by the hardware decoder utilizing contents of the first buffer, the first buffer comprising one or more instantaneous decoder refresh (IDR) frames;
• and
• when a reference frame is decoded, store the reference frame in the second buffer;
• responsive to determining that the video bit stream can not be decoded by the hardware decoder while routing the video bit stream to the hardware decoder, switch decoding from the hardware decoder to the software decoder by which the processor is configured to:
• route the video bit stream from the hardware decoder to the software decoder;
• decode the video bit stream by the software decoder using contents of the first and second buffers, the first buffer comprising the video bit stream and the second buffer comprising one or more reference frames;
• and
• when an IDR frame is decoded, store the IDR frame in the first buffer.

One or more non-transitory computer readable storage media encoded with software comprising computer executable instructions and when the software is executed operable to:

• receive a video bit stream at a hybrid decoder comprising a software decoder and a hardware decoder;
• analyze the video bit stream to determine whether or not the video bit stream can be decoded by the hardware decoder;
• responsive to determining that the video bit stream can be decoded by the hardware decoder while routing the video bit stream to the software decoder, switch decoding from the software decoder to the hardware decoder based on instructions operable to:
• route the video bit stream from the software decoder to the hardware decoder;
• store the video bit stream in a first buffer;
• decode the video bit stream by the hardware decoder utilizing contents of the first buffer, the first buffer comprising one or more instantaneous decoder refresh (IDR) frames;
• and
• when a reference frame is decoded, store the reference frame in a second buffer;
• responsive to determining that the video bit stream can not be decoded by the hardware decoder while routing the video bit stream to the hardware decoder, switch decoding from the hardware decoder to the software decoder based on instructions operable to:
• route the video bit stream from the hardware decoder to the software decoder;
• decode the video bit stream by the software decoder using contents of the first and second buffers, the first buffer comprising the video bit stream and the second buffer comprising one or more reference frames;
• and
• when an IDR frame is decoded, store the IDR frame in the first buffer.