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US 9,179,137 B2Granted
Gate driver and organic light emitting diode display including the same
AssigneeLG Display Co., Ltd.
InventorsHyunhaeng Lee, Kisu Park, Joongsun Yoon
Life of this patent
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Abstract
A gate driver and an organic light emitting diode (OLED) display including the gate driver are disclosed. The gate driver includes a shift register block including a plurality of cascade-connected shift registers, a selection block including a plurality of selection units, which are respectively connected to the plurality of shift registers, and a buffer block including a plurality of buffers, which are respectively connected to the plurality of selection units. Each of the shift registers outputs a scan pulse, whose a phase is shifted by one horizontal period, in response to a start voltage, a first clock, a second clock, and a third clock.
Claims14
A gate driver comprising:
- a shift register block including a plurality of cascade-connected shift registers, each of the plurality of shift registers configured to sequentially output a scan pulse, whose phase is shifted by one horizontal period, in response to a start voltage, a first clock, a second clock, and a third clock;
- a selection block including a plurality of selection units, the selection units respectively connected to the plurality of shift registers, wherein the plurality of selection units are configured to receive the scan pulse and the third clock as input, and each selection unit from the plurality of selection units is configured to:
- apply the scan pulse to first output nodes of the selection unit in response to a selection signal representative of a 2D mode, to sequentially set the first output nodes of the selection units at a turn-on level,
- apply the third clock to second output nodes of the selection unit in response to the selection signal of the 2D mode, to sequentially set the second output nodes of the selection units at the turn-on level,
- simultaneously set the first output nodes at the turn-on level based on a first common control signal in response to the selection signal representative of a 3D mode, and
- simultaneously set the second output nodes at the turn-on level based on a second common control signal in response to the selection signal representative of the 3D mode;
- and
- a buffer block including a plurality of buffers, the buffers respectively connected to the plurality of selection units, wherein the buffer block is configured to generate emission pulses for a sequential light emission in the 2D mode and a simultaneous light emission in the 3D mode by:
- generation of an emission pulse of a turn-off level since immediately after the first output node is set at the turn-on level to immediately before the second output node is set at the turn-on level, and
- generation of the emission pulse of the turn-on level immediately after the second output node is set at the turn-on level.
7 more elements
An organic light emitting diode (OLED) display comprising:
- a display panel including a plurality of pixels connected to a plurality of scan lines and a plurality of emission lines;
- and
- a gate driver configured to supply a scan pulse to the plurality of scan lines and supply an emission pulse to the plurality of emission lines, the gate driver including:
- a shift register block including a plurality of cascade-connected shift registers, each of the plurality of shift registers configured to output the scan pulse, whose a phase is shifted by one horizontal period, in response to a start voltage, a first clock, a second clock, and a third clock;
- a selection block including a plurality of selection units, the selection units respectively connected to the plurality of shift registers, and the plurality of selection units configured to receive the scan pulse and the third clock as input, wherein each of the plurality of selection units is configured to:
- sequentially set first output nodes and second output nodes of the selection units at a turn-on level in response to a selection signal representative of a 2D mode by application of the scan pulse to the first output nodes of the selection unit, and application of the third clock to the second output nodes of the selection unit, and
- simultaneously set the first output nodes and the second output nodes at the turn-on level in response to the selection signal representative of a 3D mode based on a first common control signal and a second common control signal;
- and
- a buffer block including a plurality of buffers, the buffers respectively connected to the plurality of selection units, the buffer block is configured to generate emission pulses for a sequential light emission in the 2D mode and a simultaneous light emission in the 3D mode, wherein each of the plurality of buffers is configured to:
- generate an emission pulse of a turn-off level since immediately after the first output node is set at the turn-on level to immediately before the second output node is set at the turn-on level, and
- generate the emission pulse of the turn-on level from immediately after the second output node is set at the turn-on level.
8 more elements
Dependencies are inferred from the claim text.