Solid-state imaging device
AssigneeKabushiki Kaisha Toshiba
InventorHiroaki Yamaoka
Life of this patent
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Abstract
According to one embodiment, a pixel array unit has pixels for accumulating photoelectric-converted charges arranged in a matrix in a row direction and a column direction; a column ADC circuit calculates, based on results of comparison between pixel signals read from the pixels and a reference voltage, AD-converted values of the pixel signals in each of columns; vertical signal wires transmit the pixel signals read from the pixels in each of the columns to the column ADC circuit; and a load circuit is dispersed in the row direction and forms source follower circuits with the pixels to read pixel signals from the pixels in each of the columns to the vertical signal wires.
Claims20
A solid-state imaging device, comprising:
- a pixel array unit in which pixels for accumulating photoelectric-converted charges are arranged in a matrix in a row direction and a column direction;
- a column ADC circuit that, based on results of comparison between pixel signals read from the pixels and a reference voltage, calculates AD-converted values of the pixel signals in each of columns;
- vertical signal wires that transmit the pixel signals read from the pixels in each of the columns to the column ADC circuit;
- and
- a load circuit that forms source follower circuits with the pixels to read pixel signals from the pixels in each of the columns to the vertical signal wire, wherein
- the load circuit includes bias voltage generation units that are dispersed in the row direction to generate bias voltages in the source follower circuits.
A solid-state imaging device, comprising:
- a pixel array unit in which pixels for accumulating photoelectric-converted charges are arranged in a matrix in a row direction and a column direction;
- a column ADC circuit that, based on results of comparison between pixel signals read from the pixels and a reference voltage, calculates AD-converted values of the pixel signals in each of columns;
- vertical signal wires that transmit pixel signals read from the pixels in each of the columns to the column ADC circuit;
- and
- a load circuit that forms source follower circuits with the pixels to read the pixel signals from the pixels in each of the columns to the vertical signal wires, wherein the load circuit includes:
- a first bias voltage generation unit that generates bias voltages in the source follower circuits;
- and
- a second bias voltage generation unit that generates bias voltages in the source follower circuits.
Dependencies are inferred from the claim text.