Post-silicon repair of on-die networks
AssigneeOracle International Corporation
InventorsRobert P Masleid, Paul J Dickinson, Murali M R Gala, Karl P Dahlgren
Life of this patent
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Abstract
A method and apparatus for post-silicon repair of on-die networks is disclosed. In one embodiment, an integrated circuit includes a first network node of an on-chip network configured to couple each of a plurality of functional units to at least one other one of the plurality of functional units. The first network node includes a plurality of ports. Each of the plurality of ports includes a plurality of multiplexers configured to substitute a spare channel of the network node into the network responsive to a test determining that another one of a plurality of channels is defective.
Claims14
A method comprising:
- testing an on-chip network of an integrated circuit, wherein the on-chip network is configured to couple each of a plurality of functional units to at least one other one of the plurality of functional units, wherein testing the on-chip network comprises testing a first network node, wherein the first network node includes a plurality of ports each having N external connections and N+1 internal connections, wherein each of the N+1 internal connections is coupled to channel circuitry corresponding to a particular bit of the on-chip network and further includes testing channel circuitry coupled to N of the N+1 internal connections of the network node and excludes testing channel circuitry coupled to the (N+1)th internal connections;
- responsive to determining that a particular channel of the on-chip network is defective, reconfiguring the on-chip network to connect a spare channel into the on-chip network using a plurality of multiplexers in a network node of the on-chip network, wherein the on-chip network includes a plurality of network nodes including the first network node, wherein shifting around the particular channel further comprises multiplexers in each port of each of the plurality of network nodes coupling channel circuitry coupled to the (N+1)th internal connection to one of the N external connections and further comprises multiplexers decoupling circuitry associated with the defective channel.
A processor comprising:
- a plurality of processor cores;
- and
- an on-chip network configured to provide an N-bit connection for each of the plurality of processor cores to any other one of the plurality of processor cores, wherein the on-chip network includes one or more network nodes, wherein each of the one or more network nodes includes:
- N channels, wherein each of the N channels includes logic circuitry corresponding to a one of the N bits of the N-bit connection;
- a spare channel including logic circuitry corresponding to a spare bit;
- a plurality of ports, wherein each of the plurality of ports includes a plurality of multiplexers configured to, responsive to a test determining that one of the N channels is defective, disconnect the defective one of the N channels from and connect the spare channel.
Dependencies are inferred from the claim text.