Partial response equalizer and related method
AssigneeRambus Inc.
InventorsChintan S. Thakkar, Kun-Yung Chang, Ting Wu
Life of this patent
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Abstract
A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
Claims20
An integrated circuit, comprising:
- a receiver to sample a signal arriving via a channel using a multiphase partial response decision feedback equalization circuit (PrDFE);
- circuitry to latch data values for each data phase of the multi-data phase PrDFE as outputs of the multiphase PrDFE;
- and
- circuitry to receive a sampling clock, and to select a phase for said sampling clock according to which the data values are to be sampled from the multi-data PrDFE, the phase being selected in dependence on timing associated with the operation of the multiphase PrDFE.
An integrated circuit for use in a signaling system where the integrated circuit is to receive a digital signal that conveys data on a channel at a rate of at least one gigabits per second, the integrated circuit comprising:
- a receiver to sample bits arriving on a channel using a multiphase partial response decision feedback equalization (PrDFE) circuit, wherein the multiphase PrDFE circuit comprises a multiplexer for each phase of said multiphase PrDFE, and wherein an output of each multiplexer is coupled to a selection input of the multiplexer for another phase of said multiphase PrDFE, in a manner uninterrupted by any form of clocked delay;
- circuitry to sample data values for each data phase of the multi-data phase PrDFE to provide outputs of the multi-phase PrDFE according to at least one sampling clock signal, the data values representing respective ones of the bits;
- and
- circuitry to select a phase said at least one sampling clock signal, the phase being selected in dependence on timing associated with the outputs of said multiplexers, the data values to be sampled from the multi-data PrDFE according to each selected phase for said at least one sampling clock signal.
An integrated circuit for use in a signaling system where the integrated circuit is to receive on each channel of at least one channel a digital signal that conveys data at a rate of at least one gigabits per second, the integrated circuit comprising:
- for each channel
- a receiver to sample bits arriving on the channel using a multiphase partial response decision feedback equalization (PrDFE) circuit, wherein the multiphase PrDFE circuit comprises a multiplexer for each phase of said multiphase PrDFE, and wherein an output of each multiplexer is coupled to a selection input of the multiplexer for another phase of said multiphase PrDFE, in a manner uninterrupted by any form of clocked delay, and
- circuitry to sample data values for each data phase of the multi-data phase PrDFE to provide outputs of the multi-phase PrDFE according to at least one sampling clock signal, the data values representing respective ones of the bits;
- and
- circuitry to select, for each clock signal of the at least one sampling clock signal, a phase, the phase being selected in dependence on timing associated with the outputs of said multiplexers, the data values to be sampled from the multi-data PrDFE according to each selected phase for said at least one sampling clock signal.
Dependencies are inferred from the claim text.