Multi-band interconnect for inter-chip and intra-chip communications

An apparatus for memory interfacing, comprising:

• a baseband receiver of a first frequency within a second integrated circuit configured for connection to a transmission line adapted for connection to a first integrated circuit;
• wherein said baseband receiver is configured for outputting a digital baseband signal in response to receiving and converting a received baseband signal through said transmission line;
• and
• at least one RF receiver, configured for connection to said transmission line for receiving and converting an amplitude shift keyed (ASK) RF signal having a carrier at a second frequency to a digital RF band output;
• wherein multiple bands, including a baseband and at least one amplitude shift keyed RF band, are simultaneously communicated from the first integrated circuit to said second integrated circuit.

A system for memory interfacing, comprising:

• a first integrated circuit device;
• a second integrated circuit device;
• a transmission line adapted for connection between said first integrated circuit device and said second integrated circuit device;
• a baseband transmitter at a first frequency within said first integrated circuit device and a baseband receiver within said second integrated circuit device, or said baseband transmitter at a first frequency within said second integrated circuit device and said baseband receiver within said first integrated circuit device;
• wherein said baseband transmitter is configured for outputting a baseband signal in response to receipt of a first data stream;
• and
• at least one RF transmitter within said first integrated circuit device and/or said second integrated circuit device having a carrier at a second frequency which is amplitude shift keyed (ASK) and configured for connection to said transmission line;
• wherein multiple bands, including a baseband and at least one amplitude shift keyed RF band, are simultaneously communicated between said first integrated circuit device and said second integrated circuit device.

An apparatus for chip-to-chip memory interfacing, comprising:

• at least one baseband transmitter at a first frequency within a first integrated circuit configured for connection to an off-chip transmission line;
• wherein said at least one baseband transmitter is configured for outputting a baseband signal in response to receipt of a first data stream within said first integrated circuit;
• and
• at least one RF transmitter within a second integrated circuit coupled to said off-chip transmission line, and having a carrier at a second frequency modulated by amplitude shift keying (ASK) in response to receipt of a second data stream;
• wherein simultaneous bi-directional communication of said first data stream and said second data stream over multiple bands is performed between said first integrated circuit and said second integrated circuit.

A system for chip-to-chip communication between integrated circuits, comprising:

• at least one baseband transmitter at a first frequency within a first integrated circuit configured for connection to a differential pair of off-chip transmission lines adapted for connection to a second integrated circuit;
• wherein said at least one baseband transmitter is configured for outputting a baseband signal in response to receipt of a first data stream within said first integrated circuit;
• and
• at least one RF transmitter, within said first integrated circuit or said second integrated circuit configured for amplitude shift keying (ASK) of a carrier at a second frequency which is coupled to said pair of off-chip transmission lines;
• wherein multiple bands, including a baseband and at least one amplitude shift keyed RF band, are simultaneously communicated chip-to-chip between integrated circuits.

An apparatus for chip-to-chip memory interfacing, comprising:

• a memory controller having multiple cores configured for communicating with multiple memory devices;
• a baseband receiver in each of said multiple cores in said memory controller is coupled to at least one of a plurality of differential transmission lines;
• and
• a plurality of RF transmitters, configured for amplitude shift keying (ASK) of a carrier generated from a voltage controlled oscillator shared between said plurality of RF transmitters, with each of said plurality of RF transmitters coupled to at least one of said plurality of differential transmission lines;
• and
• wherein said memory controller communicates with said multiple memory devices over each of said plurality of differential transmission lines using simultaneous transmissions which include a baseband and at least one amplitude shift keyed RF band.

A memory module, comprising:

• an interface router having a multiband interconnection with simultaneous baseband and amplitude shift keyed RF band transmissions for receiving data and address information from outside of said memory module;
• and
• a plurality of memory devices within said memory module coupled to said interface router;
• wherein said data and address information are received over the multiband interconnection with simultaneous baseband and amplitude shift keyed RF band transmissions and communicated with said plurality of memory chips.