Serial link training method and apparatus with deterministic latency
AssigneeBroadcom Corporation
InventorShankar Channabasappa
Life of this patent
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Abstract
A method is disclosed for handling packet data. The method includes assembling request packets for transmission along a plurality of serial lanes. For each lane, at least a portion of the request packets are framed into a request link frame having a plurality of words. The request link frame is defined by a preset word length. Request training words are inserted into the request link frame at intervals corresponding to the preset word length. Response packets are queued, where the response packets include response training words having an associated latency based on the programmed interval of the request training words.
Claims17
A method, comprising:
- assembling request packets for transmission along a plurality of serial lanes;
- and for each lane:
- framing at least a portion of the request packets into a request link frame having a plurality of words, the request link frame being defined by a preset word length;
- inserting request training words into the request link frame at intervals corresponding to the preset word length;
- queuing for response packets, the response packets including response training words having an associated deterministic latency based on a programmed interval of the request training words;
- and
- assigning processing timeslots for the response packets based on the programmed interval of the request training words.
An integrated circuit for communicating with a look-aside processor via a serial link interface, the integrated circuit comprising:
- a request pipeline having an output to transmit request data words to the look-aside processor, the request data words being organized into periodically repeating request link frames of a predefined word length;
- and
- a response pipeline having an input to receive response data words at a predetermined time after sending associated request data words, the response data words being organized, for each link, into link frames that are transmitted from the look-aside processor based on when the request link frames are received at the look-aside processor;
- wherein the response pipeline includes queuing logic to assign processing timeslots based on a deterministic latency of response packets.
An integrated circuit for communicating with a network processor via a serial link interface, the integrated circuit comprising;
- a request pipeline configured to receive request data words from the network processor, wherein the request data words are organized into periodically repeating request link frames of a predefined word length;
- a link frame detector configured to identify a start of a request link frame comprising a plurality of words of a predefined word length;
- a training word generator configured to insert response training words into a response link frame;
- and
- a response pipeline output configured to send the response link frame to the network processor in response to detecting the start of the request link frame, wherein the response link frame has a response training word latency corresponding to a request training word latency.
A system, comprising:
- a first electronic device having a request transmitter for transmitting periodic request packets in accordance with a serial protocol and a receiver for receiving response packets;
- a serial link having one end coupled to the first electronic device to route the request packets;
- and
- a second electronic device having a receiver circuit coupled to a second end of the serial link to receive the request packets and a response transmitter for transmitting the response packets to the first electronic device;
- wherein the first electronic device and the second electronic device cooperate to form respective request and response paths having associated request and response path latencies;
- wherein the response path latency is based on the request path latency;
- and
- wherein the first electronic device includes queuing logic to assign processing timeslots based on a deterministic latency.
Dependencies are inferred from the claim text.