Receiver with clock recovery circuit and adaptive sample and equalizer timing
AssigneeRambus Inc.
InventorsQi Lin, Brian Leibowitz, Hae-Chang Lee, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe
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Abstract
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
Claims19
A receiver comprising:
- an equalizer to receive a data signal and issue an equalized signal;
- a reference sampler to sample the data signal before the equalizer to produce reference samples;
- clock recovery circuitry to recover a reference clock signal from the reference samples;
- an adaptive phase-offset controller to receive the recovered reference clock signal and produce a data clock signal phase adjusted with respect to the recovered reference clock signal;
- and
- a data sampler to sample the equalized signal, after the equalizer and timed to the data clock signal, to produce data samples;
- wherein the reference sampler samples the data signal timed to the recovered reference clock signal.
A method comprising:
- receiving an input signal expressing a series of data symbols;
- equalizing the input signal to produce a series of equalized data symbols;
- sampling the input signal, before the equalizing and timed to a reference clock signal, to produce a series of reference samples;
- sampling the series of equalized data symbols, after the equalizing and timed to a data clock signal, to produce a series of data samples;
- recovering the reference clock signal from the series of reference samples;
- deriving the data clock signal from the reference clock signal;
- and
- phase adjusting the data clock signal relative to the reference clock signal while sampling the input signal timed to the reference clock signal.
A receiver instantiated on an integrated circuit, the receiver comprising:
- clock recovery circuitry to recover a reference clock signal from an input signal expressing a series of data symbols, the clock recovery circuitry including a reference sampler timed to the reference clock signal;
- a decision-feedback equalizer to produce an equalized signal from the input signal, the decision-feedback equalizer timed to a second clock signal;
- a data sampler to sample the equalized signal to produce a series of data samples;
- and
- a controller to phase adjust the second clock signal with respect to the reference clock signal;
- wherein the clock recovery circuitry recovers the reference clock signal from the input signal provided to the decision-feedback equalizer.
Dependencies are inferred from the claim text.