Snr improvement circuit, synchronization information detection circuit, communication device, snr improvement method, and synchronization information detection method

#The present invention relates to an SNR (Signal to Noise Ratio) improvement circuit, a synchronization information detection circuit, a communication device, an SNR improvement method, and a synchronization information detection method.

#Generally, in packet-type communication, a receiving-side device does not grasp when a transmitting-side device will transmit a packet, namely when a packet will arrive at the receiving-side device. Hence the receiving-side device needs to stand by for a packet to come, and detect a packet out of signals received during the standby. Further, in order to appropriately perform a variety of processing on the received packet, it is necessary to perform a variety of processing in synchronization with a configuration of the packet. Such synchronization is performed with respect to each received packet, namely every time a packet is detected.

#For example, Patent Document 1 describes a symbol timing detection circuit for an OFDM (Orthogonal Frequency Division Multiplexing) demodulator.

#FIG. 1 is a block diagram giving an outline of a communication device according to a first embodiment.

#FIG. 2 is a diagram giving an outline of a packet configuration according to the first embodiment.

#FIG. 3 is a block diagram showing constitutional examples of a timing detection processing circuit and an SNR improvement circuit according to the first embodiment.

#FIG. 1 shows a block diagram giving an outline of a communication device 1 according to a first embodiment. Although a case will be exemplified here in which the communication device 1 is a wireless communication device conforming to OFDM, this case is not restrictive.

#The communication device 1 has at least a reception function. That is, the communication device 1 is a receive-only device or a transmitting/receiving device. In the example of FIG. 1, the communication device 1 has a synchronization timing detection circuit (i.e., synchronization information detection circuit) 2 which constitutes part of the reception function, and the synchronization timing detection circuit 2 has a timing detection processing circuit (i.e., synchronization information detection processing circuit) 3 and an SNR improvement circuit 4.

#The synchronization timing detection circuit 2 performs predetermined processing on a reception signal, to detect as synchronization information the timing for synchronization with a packet contained in the reception signal, and generates and outputs a synchronization timing signal for providing the detected timing. The synchronization timing signal is used for a variety of processing (e.g., FFT (Fast Fourier Transform) computing) on a received packet. It is to be noted that the synchronization timing detection circuit 2 constitutes part of a physical layer (first layer) of a so-called OSI (Open System Interconnection) reference model.