Self-testing integrated circuits

#The embodiments discussed herein are generally related to self-testing integrated circuits.

#With the increase in internet traffic and demand for high-bandwidth applications such as high-performance computing, data-center connectivity and video content distribution, total aggregate bit rate in integrated circuits (ICs) is increasing both in line rate and number of parallel channels. This drives the need to test ICs at maximum operating rate in order to guarantee high yield in the product. Current Automatic Test Equipment (ATE) is not capable for this type of test both in bandwidth and in number of channels. Without the capability of full-speed test at the ATE level, one will either have to take a yield loss in final assembly, or to attach high-speed add-ons to the ATE or to introduce a second insertion on a test platform that has the full-speed capability. All of the aforementioned solutions add costs to the IC and/or the product in which it is used. Hence there is a need for a low-cost, full-speed self-test.

#The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced.

#To further clarify the above and other advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

#FIG. 1 is a block diagram of an example self-testing IC;

#FIG. 2 is a block diagram of an example self-testing IC that may correspond to the IC of FIG. 1; and

#Some embodiments described herein relate to self-testing ICs that include multiple channels. Each channel may include a clock and data recovery circuit (CDR). Accordingly, an example embodiment of the self-testing IC is a multichannel CDR. To accommodate full-speed self-testing, embodiments disclosed herein may further include additional circuits used in the self-testing. For example, to test for locking and error-free operation, each channel may include a pseudorandom bit stream (PRBS) generator and a PRBS checker. For applications that include a referenceless CDR under normal operation, each of the CDRs may have a test mode in which the CDRs can accept a reference clock at a relatively lower speed, such as at ¼, ⅛, 1/16 speed, or the like, and can generate and check PRBS patterns at full rate. To test for output waveform shaping features and input equalization, each CDR may include eye quality monitoring capabilities. Example embodiments of an IC that includes such capabilities and a method of operation thereof are provided in additional detail below.

#Some embodiments of multichannel self-testing ICs described herein may be implemented in a variety of operating environments. For instance, multichannel self-testing ICS as described herein may be included in multichannel optoelectronic transceiver and/or transponder modules and/or in other operating environments.

#Reference will now be made to the drawings to describe various aspects of example embodiments of the invention. It is to be understood that the drawings are diagrammatic and schematic representations of such example embodiments, and are not limiting of the present invention, nor are they necessarily drawn to scale.