US 9,178,653 B2 · Very short size LDPC coding for physical and/or control channel signaling

Abstract

A communication device is configured to encode and/or decode low density parity check (LDPC) coded signals. Such LDPC coded signals are characterized by LDPC matrices having a particular form. An LDPC matrix may be partitioned into a left hand side matrix and the right hand side matrix. The right hand side matrix can be lower triangular such that all of the sub-matrices therein are all-zero-valued sub-matrices (e.g., all of the elements within an all-zero-valued sub-matrix have the value of “0”) except for those sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to the left of the main diagonal. A device may be configured to employ different LDPC codes having different LDPC matrices for different LDPC coded signals. The different LDPC matrices may be based generally on a common form (e.g., with a right hand side matrix as described above).

Drawings

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Drawings

Claims20

Dependent claims

A communication device comprising:

a communication interface;
and
a processor, at least one of the processor or the communication interface configured to:
encode information bits using a low density parity check (LDPC) code to generate coded bits, wherein the LDPC code is characterized by an LDPC matrix that includes a plurality of sub-matrices arranged in a left hand side matrix and a right hand side matrix, wherein the right hand side matrix is lower triangular and includes all-zero-valued sub-matrices except for CSI (Cyclic Shifted Identity) sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to a left of the main diagonal;
and
puncture a subset of the information bits and a subset of parity bits from the coded bits to generate a codeword;
and
transmit a signal that includes the codeword to another communication device via a communication channel.

5 more elements

A communication device comprising:

a communication interface;
and
a processor, at least one of the processor or the communication interface configured to:
encode first information bits using a first low density parity check (LDPC) code to generate first coded bits;
encode second information bits using a second LDPC code to generate second coded bits, wherein at least one of the first or second LDPC codes is characterized by an LDPC matrix that includes a plurality of sub-matrices arranged in a left hand side matrix and a right hand side matrix, wherein the right hand side matrix is lower triangular and includes all-zero-valued sub-matrices except for CSI (Cyclic Shifted Identity) sub-matrices located on a main diagonal of the right hand side matrix and another diagonal that is adjacently located to a left of the main diagonal;
and
puncture a first subset of the first information bits and a first subset of parity bits from the first coded bits to generate a first codeword;
and
puncture a second subset of the second information bits and a second subset of parity bits from the second coded bits to generate a second codeword;
and
transmit a first signal that includes the first codeword to another communication device via a Physical Layer (PHY) Link Control (PLC) sub-channel of a communication channel;
and
transmit a second signal that includes the second codeword to the another communication device via a Next Codeword Pointer (NCP) sub-channel of the communication channel.

10 more elements

Dependencies are inferred from the claim text.

Description9,833 words

Summary354 words

#1. Technical Field

#The present disclosure relates generally to communication systems; and, more particularly, to forward error correction (FEC) and/or error correction code (ECC) coding within such communication systems.

#2. Description of Related Art

Brief description of the drawings18 figures

#FIG. 1 is a diagram illustrating an embodiment of one or more communication systems.

#FIG. 2 is a diagram illustrating another embodiment of one or more communication systems.

#FIG. 3A is a diagram illustrating a communication device operative within one or more communication systems.

Detailed description9,170 words

#FIG. 1 is a diagram illustrating an embodiment 100 of one or more communication systems. One or more network segments 190 provide communication inter-connectivity for at least two communication devices 110 and 120. Generally speaking, any desired number of communication devices is included within one or more communication systems (e.g., as shown by communication device 130). Some or all the various communication devices 110-130 include capability to operate using forward error correction (FEC) and/or error correction code (ECC) as described herein.

#The various communication links within the one or more network segments 190 may be implemented using any of a variety of communication media including communication links implemented as wireless, wired, optical, satellite, microwave, etc. communication links. Also, in some instances, communication links of different types may cooperatively form a connection pathway between any two communication devices. Considering one example, a communication pathway between devices 110 and 120 may include some segments of wired communication links and other segments of optical communication links. Note also that the devices 110-130 may be of a variety of types of devices including stationary devices, mobile devices, portable devices, etc. and may support communications for any of a number of services or service flows including data, telephony, television, Internet, media, synchronization, etc.

#In an example of operation, device 110 includes a communication interface to support communications with one or more of the other devices 120-130. This communication may be bidirectional/to and from the one or more of the other devices 120-130 or unidirectional (or primarily unidirectional) to or from the one or more of the other devices 120-130.

Facts

Application

14/068,534Filed 31 Oct 2013 · us provisional application

Priority

16 Jan 2013

Published

US 2014/0201592 A117 Jul 2014

Granted

3 Nov 2015

Term ends

10 Jan 2034

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 71 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification11 codes

H04L 1/0041
By using forward error control: arrangements at the transmitter end
H03M 13/1137
Scheduling of bit node or check node processing: partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
H03M 13/116
Structural properties of the code parity-check or generator matrix: quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed…
H03M 13/118
Structural properties of the code parity-check or generator matrix: parity check matrix structured for simplifying encoding, e.g. by having a…

Family

Application61/753,267Us provisional application · filed 16 Jan 2013

Application61/768,035Us provisional application · filed 22 Feb 2013

Application61/809,647Us provisional application · filed 8 Apr 2013

Application61/820,651Us provisional application · filed 7 May 2013

Application61/822,871Us provisional application · filed 13 May 2013

Application61/825,322Us provisional application · filed 20 May 2013

Application61/834,825Us provisional application · filed 13 Jun 2013

Application61/886,136Us provisional application · filed 3 Oct 2013

US 2014/0201592 A1Pre-grant publication · published 17 Jul 2014

US 9,178,653 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

16 Jan 2013Priority claimedParent application 61/753,267
31 Oct 2013Application filedUS 14/068,534
31 Oct 2013Assigned to Broadcom Corporationassignment of assignor's interest
17 Jul 2014PublishedUS 2014/0201592 A1
3 Nov 2015GrantedUS 9,178,653 B2
11 Feb 2016Assigned to Bank of America, N.A., AS Collateral Agentpatent security agreement
1 Feb 2017Assigned to Avago Technologies General IP (Singapore) Pte. Ltd.assignment of assignor's interest
3 Feb 2017Assigned to Broadcom Corporationtermination and release of security interest in patents
4 Oct 2018Assigned to Avago Technologies International Sales Pte. Limitedmerger
29 Oct 2018Assigned to Avago Technologies International Sales Pte. Limitedcorrective assignment to correct the effective date previously recorded on reel 047229 frame 0408. assignor(s) hereby confirms the the effective date is 09/05/2018.
22 Mar 2019Assigned to Avago Technologies International Sales Pte. Limitedcorrective assignment to correct the patent number 9,385,856 to 9,385,756 previously recorded at reel: 47349 frame: 001. assignor(s) hereby confirms the merger.
12 Oct 2026TodayWithin its term
10 Jan 2034Term endsEstimated, includes 71 days of adjustment

Very short size LDPC coding for physical and/or control channel signaling

Life of this patent

Very short size LDPC coding for physical and/or control channel signaling

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims20

Description9,833 words

Drawings

Classification11 codes

Life of this patent

Description9,833 words