Voltage regulator for a serializer/deserializer communication application

#The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer device. But it will be recognized that the technique can be used for regulating memory devices (e.g., double data rate fourth generation (DDR4) synchronous dynamic random-access memory (SDRAM) devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications.

#As integrated circuits are designed to operate at increasingly higher frequencies, noisy, distorted, and/or inconsistent signals can cause devices such as output drivers to produce poor quality output. Preferably, an output driver may provide a clean, symmetric, well-shaped output waveform even if the input signals are noisy or of poor quality. However, a driver may receive an asymmetric, low quality differential signal with a substantial and/or inconsistent amplitude variation and/or a common mode component. In many cases, the quality of the differential input signal may degrade with increased operating frequency. An eye diagram, constructed by overlaying the output voltage waveforms for many clock cycles, may be used indicate the fidelity or quality of a signal put through an electronic buffer circuit. A high quality output waveform may have an eye diagram with a symmetric shape that approaches the shape of a square wave. Often, it is desirable to have an output waveform with a centered or controllable crossing point (the point where the rising and falling signals intersect). The output crossing point may be characterized by the crossing point voltage. For a differential output, each of the output waveforms has an associated crossing point voltage.

#From the above, it is seen that techniques for improving output waveforms and regulating them are highly desirable.

#The following diagrams are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many other variations, modifications, and alternatives. It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this process and scope of the appended claims.

#FIG. 1 is a simplified block diagram of a SerDes block diagram according to an embodiment of the present invention;

#FIG. 2 is a more detailed block diagram of a transmitter module according to an embodiment of the present invention;

#The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.

#A limitation in optical networking is the development of low-power transceivers that interface to optical sub-assemblies, e.g., transmitter or receiver optical subassembly (TOSAs & ROSAs). Whilst SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches [1]. This specification describes a generic CMOS 25-30 Gb/s SerDes for use within clock data recovery (CDR) or gearbox applications, targeting the draft requirements of the OIF 28G-VSR (very short reach) standard [2] and suitable for both 100 GBASE-LR4/OTL4.4 gearbox & retiming applications, including CFP & CFP2 [3].

#A block diagram of the SerDes is shown in FIG. 1. Two phase locked loops (PLLs) (separated for TX & RX to support a line retiming mode) with four quadrature 7.0 GHz phases for 28 Gb/s operation provide reference timing edges for both the transmitter & receiver. These are distributed using two sets of four on-chip transmission lines. Transmission line techniques minimize power consumption and timing skew between the four clock phases, this in turn reduces the requirements on the quadrature and duty-cycle correction of the clock phases. A MDIO (Management Data Input/Output) interface provides control of both transmitter & receiver and selection of diagnostic & debug modes. An additional electrical fuse interface (not shown) provides non-volatile storage for a range of programmable MDIO defaults and also manufacturing trim settings for the bandgap reference and regulators.