Mismatch corrector
AssigneeTexas Instruments Incorporated
InventorsSthanunathan Ramakrishnan, Sreenath Narayanan Potty
Life of this patent
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Abstract
A mismatch corrector can include a correction path comprising a plurality of parallel branches that each includes a correction filter that applies a respective one of a plurality of time domain filter coefficients that corresponds to a function of a mismatch profile of an interleaved analog-to-digital (IADC) signal on the IADC signal. The mismatch corrector can also include a delay path that delays the IADC signal by a predetermined number of samples to provide a delayed version of the IADC signal. The mismatch corrector can further include a summer to subtract an output of each correction filter from the delayed version of the IADC signal to generate a corrected IADC signal.
Claims22
A mismatch corrector comprising:
- a correction path comprising a plurality of parallel branches that each comprises a correction filter that applies a respective one of a plurality of time domain filter coefficients that corresponds to a function of a mismatch profile of an interleaved analog-to-digital (IADC) signal on the IADC signal;
- a delay path that delays the IADC signal by a predetermined number of samples to provide a delayed version of the IADC signal;
- and
- a summer to subtract an output of each correction filter from the delayed version of the IADC signal to generate a corrected IADC signal.
An integrated circuit (IC) chip comprising:
- an interleaved analog-to-digital converter (ADC) comprising M number of component ADCs that are each configured to sample an analog signal in response to a clock pulse, wherein M is an integer greater than or equal to two and the interleaved ADC outputs an interleaved ADC (IADC) signal that comprises a plurality of spurious signals formed from mismatches between the M number of component ADCs;
- a mismatch estimator determines a frequency domain mismatch profile estimate that characterizes the mismatches between the M number of component ADCs;
- a time domain converter to convert the frequency domain mismatch profile estimate into M−1 number of filter coefficients in the time domain;
- and
- a mismatch corrector comprising M−1 number of correction filters to remove the mismatches from a delayed version of the IADC signal based on the M−1 number of filter coefficients to form a corrected IADC signal.
A method comprising:
- receiving an interleaved analog-to-digital (IADC) signal, the IADC signal comprising a plurality of image signals caused by mismatches in an interleaved analog-to-digital converter (ADC);
- receiving a plurality of filter coefficients that correspond to the mismatches in the IADC signal;
- applying correction filters to the IADC signal, wherein each correction filter implements one of the plurality of filter coefficients;
- and
- subtracting the output of each of the correction filters from a delayed version of the IADC signal to form a corrected IADC signal.
Dependencies are inferred from the claim text.