Hybrid R-2R structure for low glitch noise segmented DAC
AssigneeQUALCOMM Incorporated
InventorsSang Min Lee, Dongwon Seo
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Abstract
The apparatus may be an N-bit DAC including (2M−1) parallel stages associated with M most significant bits, and (N-M) stages associated with (N-M) least significant bits. The (2M−1) parallel stages may deliver a first current to current-summing nodes of the DAC. The (N-M) stages may include a resistive network and a second pair of switches, and may deliver a second current to the resistive network of the stage. Each resistive network may scale the respectively delivered currents according to a binary weight of a stage corresponding to the resistive network, and may deliver the scaled currents to the pair of current-summing nodes. At least one of the (N-M) stages may be separated from the remaining stages.
Claims30
An N-bit digital-to-analog converter (DAC) comprising:
- (2M−1) parallel stages associated with M most significant bits of the DAC, each stage of the (2M−1) parallel stages being configured to generate and to deliver a first current to a pair of current-summing nodes of the DAC via a first pair of switches responsive to differential data;
- and
- (N-M) stages associated with (N-M) least significant bits of the DAC, each stage of the (N-M) stages comprising a resistive network and a second pair of switches, each stage of the (N-M) stages being configured to generate and to deliver a second current via the second pair of switches to the resistive network of the stage in response to differential data, each resistive network being configured to scale the respectively delivered currents according to a binary weight of a stage corresponding to the resistive network, and to deliver the scaled currents to the pair of current-summing nodes,
- wherein at least one of the (N-M) stages is separated from all remaining stages of the N-bit DAC.
A method of converting an N-bit digital signal to an analog signal, the method comprising:
- generating a first current in each stage of (2M−1) parallel stages associated with M most significant bits of the digital signal;
- delivering each of the first currents to a pair of current-summing nodes via a first pair of switches responsive to differential data;
- generating a second current in each stage of (N-M) stages associated with (N-M) least significant bits of the digital signal, at least one of the (N-M) stages being separated from all remaining stages of the N-bit DAC;
- delivering to each network of (N-M) resistive networks the second current generated in its associated stage via a second pair of switches responsive to differential data, each network being associated with a respective one of the (N-M) stages;
- scaling the respectively delivered currents in accordance with a binary weight of a stage corresponding to the resistive network;
- delivering the scaled currents to the pair of current-summing nodes;
- maintaining an impedance of each node of the pair of current-summing nodes within a range defined by a gain value;
- and
- maintaining a voltage difference between the current-summing nodes within a range defined by the gain value, the difference in the scaled currents delivered to different nodes of the pair of current-summing nodes defining a value of the analog signal.
An N-bit digital-to-analog converter (DAC) comprising:
- (2M−1) parallel stages associated with M most significant bits of digital data;
- means for generating a first current in each stage of the (2M−1) stages;
- means for delivering the generated first current to a pair of current-summing nodes via a first pair of switches responsive to differential data;
- (N-M) stages associated with (N-M) least significant bits of the digital data such that at least one of the (N-M) stages is separated from all remaining stages of the N-bit DAC;
- means for generating a second current in each stage of the (N-M) stages;
- (N-M) resistive networks, each associated with a respective one of the (N-M) stages;
- means for delivering to each network of the (N-M) resistive networks the second current generated in its associated stage via a second pair of switches responsive to differential data;
- means for scaling the current delivered to each resistive network in accordance with a binary weight of a stage corresponding to the resistive network;
- means for delivering the scaled currents to the pair of current-summing nodes;
- means for maintaining an impedance of each node of the pair of current-summing nodes within a range defined by a gain value;
- and
- means for maintaining a voltage difference between the current-summing nodes within a range defined by the gain value, the difference in the scaled currents delivered to different nodes of the pair of current-summing nodes defining a value of an analog signal produced by the N-bit DAC.
Dependencies are inferred from the claim text.