Fast settling mixed signal phase interpolator with integrated duty cycle correction
AssigneeIntel Corporation
InventorsStefano Giaconi, Mingming Xu
Life of this patent
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Abstract
Described is an apparatus which comprises: a current steering digital-to-analog converter (DAC) to receive a digital bus to control current steering; a switch capacitor network to integrate currents from the DAC, the switch capacitor network having switches which are controllable by a plurality of digital clock signals; an output stage to compare the integrated currents against at least two threshold voltages and to generate an output signal; and a duty cycle corrector (DCC) operable to adjust the at least two threshold voltages to modify duty cycle of the output signal.
Claims20
An apparatus comprising:
- a current steering digital-to-analog converter (DAC) to receive a digital bus to control current steering;
- a plurality of switches each of which is controllable by a clock signal and each of which is coupled to the DAC, the plurality of switches are operable to provide a first current and a second current;
- an integrator which is operable to be reset, the integrator coupled to the plurality of switches;
- and
- an output stage coupled to the integrator to provide rising and falling edges of an output signal.
A phase interpolator comprising:
- a current steering digital-to-analog converter (DAC) to receive a digital bus to control current steering;
- a switch capacitor network to integrate currents from the DAC, the switch capacitor network having switches which are controllable by a plurality of digital clock signals;
- an output stage to compare the integrated currents against at least two threshold voltages and to generate an output signal;
- and
- a duty cycle corrector (DCC) operable to adjust the at least two threshold voltages to modify duty cycle of the output signal.
A system comprising:
- a memory;
- a processor coupled to the memory, the processor including a phase interpolator comprising:
- a current steering digital-to-analog converter (DAC) to receive a digital bus to control current steering;
- a plurality of switches each of which is controllable by a clock signal and each of which is coupled to the DAC, the plurality of switches are operable to provide a first current and a second current;
- an integrator which is operable to be reset, the integrator coupled to the plurality of switches;
- and
- an output stage coupled to the integrator to provide rising and falling edges of an output signal;
- and
- a wireless interface for allowing the processor to communicatively couple to another device.
Dependencies are inferred from the claim text.