US 9,178,519 B2 · Clock signal generator

Abstract

A clock generator suitable for use with memory devices enables generation of memory clock signals having odd or even division ratios, an optional phase shift and a 50% duty cycle. First and second clock gate circuits receive a base clock signal and an inverted version thereof, respectively, and are both gated by the output of two comparators that are set when a value of a down counter receiving the base clock signal reaches a predetermined value. The clock gate circuits each include a multiplexer and D-type flip-flop. The output from either flip-flop, or both their outputs ‘ORed’ together, may be used as a memory clock depending on the desired division ratio and phase shift. The generator is particularly suitable for DDR memory applications that require both edges of the clock signal are evenly placed for launching data on both rising and falling edges.

Claims17

Dependent claims

A clock generator circuit for generating a divided clock signal from a base clock signal, the clock generator circuit comprising:

a first clock gate circuit that receives the base clock signal and first and second clock gate enable signals;
a counter that receives the base clock signal;
a first comparator having a first input coupled to an output of the counter and a second input that receives a first reference value, wherein the first comparator compares the counter output value with the first reference value and generates the first clock gate enable signal;
a second comparator having a first input coupled to the output of the counter and a second input that receives a second reference value, wherein the second comparator compares the counter output value with the second reference value and generates the second clock gate enable signal;
a second clock gate circuit, coupled to the first and second comparators, that receives the base clock signal and the first and second clock gate enable signals;
and
a logic gate, coupled to outputs of the first and second clock gate circuits, that generates the divided clock signal at an output thereof.

4 more elements

A clock generator circuit for generating a divided clock signal from a base clock signal, the clock generator circuit comprising:

a counter that receives the base clock signal and generates a count value;
a first comparator that receives and compares the count value and a first reference value, and generates a first clock gate enable signal;
a second comparator that receives and compares the count value and a second reference value, and generates a second clock gate enable signal;
a first clock gate circuit, coupled to the first and second comparators, for receiving the base clock signal and first and second clock gate enable signals;
a second clock gate circuit, coupled to the first and second comparators, for receiving the base clock signal and the first and second clock gate enable signals;
and
an OR gate coupled to an output of the first clock gate circuit and an output of the second clock gate circuit, wherein the OR gate generates the divided clock signal at an output thereof.

4 more elements

Dependencies are inferred from the claim text.

Clock signal generator

Life of this patent

Clock signal generator

Life of this patent

Abstract

Claims17