Sub-threshold FPGA and related circuits and methods thereof
AssigneeUniversity of Virginia Patent Foundation
InventorsBenton H. Calhoun, Joseph F. Ryan
Life of this patent
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Abstract
A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.
Claims39
A field programmable gate array (FPGA), comprising:
- a circuit configured to operate in a sub-threshold voltage range,
- wherein said circuit has a VDD level that is less than a threshold voltage of transistors in said circuit,
- wherein said circuit employs a low-swing signaling scheme, and
- wherein said low-swing signaling scheme is a signaling with a voltage swing that is less than said VDD level.
A field programmable gate array (FPGA), comprising:
- a circuit configured to operate in a sub-threshold voltage range,
- wherein said circuit has a VDD level that is less than a threshold voltage of transistors in said circuit,
- wherein said circuit employs a low-swing signaling scheme, and
- wherein said circuit employs said low-swing signaling scheme using single passgate switches.
Dependencies are inferred from the claim text.