Memory blocks with shared address bus circuitry

An integrated circuit comprising:

• a plurality of storage circuits each having a respective address port and first and second bus ports;
• an address bus traversing at least two storage circuits of the plurality of storage circuits, wherein the address bus enters each of the traversed storage circuits at the first bus port of that storage circuit and exits each of the traversed storage circuit at the second bus port of that storage circuit;
• and
• a multiplexer coupled to the first bus port and the address port of a given storage circuit of the plurality of storage circuits, wherein the multiplexer receives a first address signal from the address port and a second address signal from the first bus port and selects from the received address signals, and wherein the selected address signal identifies a memory segment of the first storage circuit.

A method for operating an integrated circuit that includes first and second memory blocks, the method comprising:

• with the first memory block, receiving an address signal, wherein the address signal designates a memory segment in a first memory array of the first memory block;
• with an address bus, routing the address signal from the address port of the first memory block to the second memory block;
• and
• with a multiplexer of the second memory block coupled to the address bus and an address port of the second memory block, selecting an address signal to designate a memory segment in a second memory array of the second memory block that is different than the first memory array.