Differential comparator circuit having a wide common mode input range

#An embodiment of the present invention generally relates to transistor amplification, and more particularly to differential comparators.

#A difference comparator is a circuit that accepts inputs and determines a difference between them. Typical difference comparators take two inputs and return a signal indicating which of the signals is higher. Many circuits use difference comparators, such as analog to digital converters (ADC) or transceiver circuits.

#Difference comparators are commonly used in communications systems to communicate signals between different circuits. For noise-immunity reasons, most communication standards utilize differential signaling. In differential signaling, data is transmitted in the form of a differential voltage across two nodes.

#Various aspects and advantages of the invention will become apparent upon review of the following detailed description and upon reference to the drawings in which:

#FIG. 1 shows a block diagram of an example complementary diff-pair segment;

#FIG. 2 shows a graph of the gain response of typical complementary diff-pairs over a range of common mode voltages;

#Complimentary differential pair amplifiers (diff-pairs for short) are often used to perform difference comparison operations. The gain of a typical complimentary diff-pair can vary up to 50 percent when used over a range of common mode voltages. As a result, the gain must be adjusted according to the common mode used. However, this gain adjustment is undesirable as it affects the linearity of the difference comparator output. One or more embodiments of the present invention provide a method and circuit for nearly linear difference comparison that can operate across a wide common-mode input range.

#In one embodiment of the present invention, complementary diff-pairs are implemented in parallel segments to achieve a wide common-mode voltage input range. FIG. 1 shows a block diagram of an example complementary diff-pair segment. The complementary diff-pair segment includes an NMOS diff-pair 120 and a PMOS diff-pair 102. The NMOS and PMOS diff-pairs 120 and 102 respectively include NMOS transistors 124 and 126 and PMOS transistors 104 and 106 that receive differential inputs and generate tail currents 110, 112, 130, and 132. The difference between the tail currents output from each pair represents the voltage difference of the received differential inputs.

#The diff-pair circuits are biased by transistors 108 and 128 against a common mode input voltage bias to center the input signals within the linear operating range of transistors 110, 112, 130, 132. The NMOS diff-pair 120 requires a high common mode biasing. If a low common mode voltage is used, the gate voltage of transistor 128 will be near ground voltage. As a result, the tail currents allowed to pass through transistor 128 will be close to zero. The PMOS diff-pair has the opposite limitation and requires a low common mode voltage. If a high common mode voltage is used, the gate voltage of transistor 108 will be near source voltage. As a result, the tail currents allowed to pass through transistor 108 will be close to zero.