Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning

A system comprising:

• a memory unit;
• a processor coupled to the memory unit, the processor including:
• a delay line including at least four delay stages coupled together in a series;
• a first multiplexer having a first input coupled to an output of a first delay stage of the at least four delay stages, and a second input coupled to an output of a third delay stage of the at least four delay stages;
• a second multiplexer having a first input coupled to an output of a second delay stage of the at least four delay stages, and a second input coupled to an output of a fourth delay stage of the at least four delay stages;
• a phase interpolator coupled to outputs of the first and second multiplexers, the phase interpolator having an output;
• and
• a controller to generate control signals for the phase interpolator, the controller to adjust control signals in order to adjust the output periodically based on a programmable time period;
• and
• a wireless interface for allowing the processor to communicate with another device.

An apparatus comprising:

• a delay line including at least four delay stages coupled together in a series;
• a first multiplexer having a first input coupled to an output of a first delay stage of the at least four delay stages, and a second input coupled to an output of a third delay stage of the at least four delay stages;
• a second multiplexer having a first input coupled to an output of a second delay stage of the at least four delay stages, and a second input coupled to an output of a fourth delay stage of the at least four delay stages;
• a phase interpolator coupled to outputs of the first and second multiplexers, the phase interpolator having an output, wherein the phase interpolator comprises a first set of mixers that receive output of the first multiplexer and a second set of mixers that receive output of the second multiplexer;
• and
• a controller to select a different input than before for one of the first and second multiplexers when one of the first or second sets of mixers is operating at its maximum mixing range.