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US 9,178,499 B2Granted
Low-power offset-stored latch
AssigneeTexas Instruments Incorporated
InventorsMahadevan Venkiteswaran, Rajavelu Thinakaran
Life of this patent
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Abstract
A low-power offset-stored CMOS latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset storage phase and enable transistors that are arranged to couple a resolution bias current during a resolution period to a respective input pair device. The low-power offset-stored CMOS latch optionally includes current scaling to provide a resolution bias current that is larger than the predetermined bias current of the offset storage phase.
Claims20
A latch, comprising:
- an output stage having a first output and a second output, wherein the first output is arranged to provide a first positive feedback loop for controlling the second output, and wherein the second output is arranged to provide a second positive feedback loop for controlling the first output;
- and
- an input stage having a first input capacitively coupled to a control input of a first amplifier and a second input capacitively coupled to a control input of a second amplifier, wherein the first output is selectively coupled to a first signal input of the first amplifier and the second output is selectively coupled to a first signal input of the second amplifier during a resolution phase, wherein a bias current source is selectively coupled via a first resistor to the control input and to the first signal input of the first amplifier during an offset storage phase, and wherein the bias current source is selectively coupled via a second resistor to the control input and to the first signal input of the second amplifier during the offset storage phase.
A converter system, comprising:
- an output stage having a first output and a second output, wherein the first output is arranged to provide a first positive feedback loop for controlling the second output, and wherein the second output is arranged to provide a second positive feedback loop for controlling the first output;
- an input stage having a first input capacitively coupled to a control input of a first amplifier and a second input capacitively coupled to a control input of a second amplifier, wherein the first output is selectively coupled to a first signal input of the first amplifier and the second output is selectively coupled to a first signal input of the second amplifier during a resolution phase, wherein a bias current source is selectively coupled via a first resistor to the control input and to the first signal input of the first amplifier during an offset storage phase, and wherein the bias current source is selectively coupled via a second resistor to the control input and to the first signal input of the second amplifier during the offset storage phase;
- and
- a converter that is arranged to generate a sample signal and an enable signal in response to a clock signal wherein the enable signal is asserted during the resolution phase and the sample signal is asserted during the offset storage phase.
1 more element
A method of latching, comprising:
- asserting a logic state of a first output of a latch in response to a second output of the latch and asserting a logic state of the second output in response to the first output;
- capacitively coupling a first input of an input stage of the latch to a control input of a first amplifier, and capacitively coupling a second input of the input stage of the latch to a control input of a second amplifier;
- selectively coupling the first output to a first signal input of the first amplifier during a resolution phase and selectively coupling the second output to a first signal input of the second amplifier during the resolution phase;
- and
- selectively coupling a bias current source via a first resistor to the control input and to the first signal input of the first amplifier during an offset storage phase, and selectively coupling the bias current source via a second resistor to the control input and to the first signal input of the second amplifier during the offset storage phase.
2 more elements
Dependencies are inferred from the claim text.